LH28F008SCR-V85 Sharp Electronics, LH28F008SCR-V85 Datasheet - Page 14

• Manufacturer Part Number: LH28F008SCR-V85
• Manufacturer: Sharp Electronics

Specifications of LH28F008SCR-V85

• Cell Type: NOR
• Density: 8Mb
• Access Time (max): 85ns
• Interface Type: Parallel
• Boot Type: Not Required
• Address Bus: 20b
• Operating Supply Voltage (typ): 5V
• Operating Temp Range: 0C to 70C
• Package Type: TSOP-I
• Sync/async: Asynchronous
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Word Size: 8b
• Number Of Words: 1M
• Supply Current: 50mA
• Mounting: Surface Mount
• Pin Count: 40
• Lead Free Status / Rohs Status: Not Compliant

Write Suspend command (see Section 4.8), a byte
write operation can also be suspended. During a
byte write operation with block erase suspended,
status register bit SR.7 will return to "0" and the
RY/BY# output will transition to V
SR.6 will remain "1" to indicate block erase
suspend status.
The only other valid commands while block erase is
suspended are Read Status Register and Block
Erase Resume. After a Block Erase Resume
command is written to the flash memory, the WSM
will continue the block erase process. Status
register bits SR.6 and SR.7 will automatically clear
and RY/BY# will return to V
Resume
automatically outputs status register data when
read (see Fig. 5). V
same V
erase is suspended. RP# must also remain at V
or V
Block erase cannot resume until byte write
operations initiated during block erase suspend
have completed.
4.8 Byte Write Suspend Command
The Byte Write Suspend command allows byte
write interruption to read data in other flash memory
locations. Once the byte write process starts,
writing the Byte Write Suspend command requests
that the WSM suspend the byte write sequence at
a predetermined point in the algorithm. The device
continues to output status register data when read
after the Byte Write Suspend command is written.
Polling status register bits SR.7 and SR.2 can
determine when the byte write operation has been
suspended (both will be set to "1"). RY/BY# will
also transition to V
the byte write suspend latency.
At this point, a Read Array command can be
written to read data from locations other than that
which is suspended. The only other valid
HH
(the same RP# level used for block erase).
PP
level used for block erase) while block
command
OH
PP
. Specification t
must remain at V
is
written,
OL
. After the Erase
WHRH1
OL
the
. However,
PPH1/2
defines
device
(the
IH
- 14 -
commands while byte write is suspended are Read
Status Register and Byte Write Resume. After Byte
Write Resume command is written to the flash
memory, the WSM will continue the byte write
process. Status register bits SR.2 and SR.7 will
automatically clear and RY/BY# will return to V
After the Byte Write Resume command is written,
the device automatically outputs status register data
when read (see Fig. 6). V
V
while in byte write suspend mode. RP# must also
remain at V
byte write).
4.9 Set Block and Master Lock-Bit
A flexible block locking and unlocking scheme is
enabled via a combination of block lock-bits and a
master lock-bit. The block lock-bits gate program
and erase operations while the master lock-bit
gates block-lock bit modification. With the master
lock-bit not set, individual block lock-bits can be set
using the Set Block Lock-Bit command. The Set
Master Lock-Bit command, in conjunction with RP#
= V
lock-bit is set, subsequent setting of block lock-bits
requires both the Set Block Lock-Bit command and
V
hardware and software write protection options.
Set block lock-bit and master lock-bit are executed
by a two-cycle command sequence. The set block
or master lock-bit setup along with appropriate
block or device address is written followed by either
the set block lock-bit confirm (and an address
within the block to be locked) or the set master
lock-bit confirm (and any device address). The
WSM then controls the set lock-bit algorithm. After
the sequence is written, the device automatically
outputs status register data when read (see Fig. 7).
The CPU can detect the completion of the set lock-
bit event by analyzing the RY/BY# pin output or
status register bit SR.7.
PPH1/2
HH
HH
on the RP# pin. See Table 5 for a summary of
, sets the master lock-bit. After the master
Commands
(the same V
IH
or V
HH
PP
(the same RP# level used for
LH28F008SC-V/SCH-V
level used for byte write)
PP
must remain at
OL
.