LH28F008SCR-V85 Sharp Electronics, LH28F008SCR-V85 Datasheet - Page 8

• Manufacturer Part Number: LH28F008SCR-V85
• Manufacturer: Sharp Electronics

Specifications of LH28F008SCR-V85

• Cell Type: NOR
• Density: 8Mb
• Access Time (max): 85ns
• Interface Type: Parallel
• Boot Type: Not Required
• Address Bus: 20b
• Operating Supply Voltage (typ): 5V
• Operating Temp Range: 0C to 70C
• Package Type: TSOP-I
• Sync/async: Asynchronous
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Word Size: 8b
• Number Of Words: 1M
• Supply Current: 50mA
• Mounting: Surface Mount
• Pin Count: 40
• Lead Free Status / Rohs Status: Not Compliant

array mode. Four control pins dictate the data flow
in and out of the component : CE#, OE#, WE#,
and RP#. CE# and OE# must be driven active to
obtain data at the outputs. CE# is the device
selection control, and when active enables the
selected memory device. OE# is the data output
(DQ
selected memory data onto the I/O bus. WE# must
be at V
illustrates a read cycle.
3.2 Output Disable
With OE# at a logic-high level (V
outputs are disabled. Output pins DQ
placed in a high-impedance state.
3.3 Standby
CE# at a logic-high level (V
standby mode which substantially reduces device
power consumption. DQ
in a high-impedance state independent of OE#. If
deselected during block erase, byte write, or lock-bit
configuration, the device continues functioning, and
consuming active power until the operation
completes.
3.4 Deep Power-Down
RP# at V
In read modes, RP#-low deselects the memory,
places output drivers in a high-impedance state and
turns off all internal circuits. RP# must be held low
for a minimum of 100 ns. Time t
after return from power-down until initial memory
access outputs are valid. After this wake-up
interval, normal operation is restored. The CUI is
reset to read array mode and status register is set
to 80H.
0
-DQ
IH
IL
7
and RP# must be at V
) control and when active drives the
initiates the deep power-down mode.
0
-DQ
IH
) places the device in
7
outputs are placed
IH
PHQV
or V
IH
), the device
HH
is required
0
-DQ
. Fig. 12
7
are
- 8 -
During block erase, byte write, or lock-bit
configuration modes, RP#-low will abort the
operation. RY/BY# remains low until the reset
operation is complete. Memory contents being
altered are no longer valid; the data may be
partially erased or written. Time t
after RP# goes to logic-high (V
command can be written.
As with any automated device, it is important to
assert RP# during system reset. When the system
comes out of reset, it expects to read from the flash
memory. Automated flash memories provide status
information when accessed during block erase, byte
write, or lock-bit configuration modes. If a CPU
reset occurs with no flash memory reset, proper
CPU initialization may not occur because the flash
memory may be providing status information
instead of array data. SHARP
allow proper CPU initialization following a system
reset through the use of the RP# input. In this
application, RP# is controlled by the same RESET#
signal that resets the system CPU.
LH28F008SC-V/SCH-V
’
IH
s flash memories
PHWL
) before another
is required