LH28F008SCR-V85 Sharp Electronics, LH28F008SCR-V85 Datasheet - Page 5

• Manufacturer Part Number: LH28F008SCR-V85
• Manufacturer: Sharp Electronics

Specifications of LH28F008SCR-V85

• Cell Type: NOR
• Density: 8Mb
• Access Time (max): 85ns
• Interface Type: Parallel
• Boot Type: Not Required
• Address Bus: 20b
• Operating Supply Voltage (typ): 5V
• Operating Temp Range: 0C to 70C
• Package Type: TSOP-I
• Sync/async: Asynchronous
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Word Size: 8b
• Number Of Words: 1M
• Supply Current: 50mA
• Mounting: Surface Mount
• Pin Count: 40
• Lead Free Status / Rohs Status: Not Compliant

1 INTRODUCTION
This datasheet contains LH28F008SC-V/SCH-V
specifications. Section 1 provides a flash memory
overview. Sections 2, 3, 4, and 5 describe the
memory organization and functionality. Section 6
covers electrical specifications. LH28F008SC-V/
SCH-V flash memories documentation also
includes ordering information which is referenced in
Section 7.
1.1 New Features
LH28F008SC-V/SCH-V Smart 5 flash memories
maintain
LH28F008SA.
LH28F008SA include :
Both devices share a compatible pinout, status
register, and software command set. These
similarities enable a clean upgrade from the
LH28F008SA to LH28F008SC-V/SCH-V. When
upgrading, it is important to note the following
differences :
1.2 Product Overview
The LH28F008SC-V/SCH-V are high-performance
8 M-bit Smart 5 flash memories organized as 1 M-
byte of 8 bits. The 1 M-byte of data is arranged in
sixteen 64 k-byte blocks which are individually
• Smart 5 Technology
• Enhanced Suspend Capabilities
• In-System Block Locking
• Because of new feature support, the two
• V
• To take advantage of Smart 5 technology, allow
devices have different device codes. This
allows for software optimization.
support 5 V block erase, byte write, and lock-bit
configuration operations. Designs that switch
V
sure that the V
V
PPLK
PP
PP
connection to 5 V.
off during read operations should make
has been lowered from 6.5 V to 1.5 V to
backwards-compatibility
Key
PP
voltage transitions to GND.
enhancements
with
over
the
the
- 5 -
erasable, lockable, and unlockable in-system. The
memory map is shown in Fig.1.
Smart 5 technology provides a choice of V
V
system performance and power expectations. V
at 5 V eliminates the need for a separate 12 V
converter, while V
and byte write performance. In addition to flexible
erase and program voltages, the dedicated V
gives complete data protection when V
Internal V
matically configures the device for optimized read
and write operations.
A Command User Interface (CUI) serves as the
interface between the system processor and
internal operation of the device. A valid command
sequence written to the CUI initiates device
automation. An internal Write State Machine (WSM)
automatically executes the algorithms and timings
necessary for block erase, byte write, and lock-bit
configuration operations.
A block erase operation erases one of the device’s
64 k-byte blocks typically within 1 second (5 V V
12 V V
can be independently erased 100 000 times (1.6
million block erases per device). Block erase
suspend mode allows system software to suspend
block erase to read data from, or write data to any
other block.
Writing memory data is performed in byte
increments typically within 6 µs (5 V V
V
PP
PP
Table 1 V
). Byte write suspend mode enables the system
combinations, as shown in Table 1, to meet
V
PP
CC
) independent of other blocks. Each block
VOLTAGE
CC
5 V
CC
Offered by Smart 5 Technology
and V
and V
PP
= 12 V maximizes block erase
PP
PP
LH28F008SC-V/SCH-V
detection circuitry auto-
Voltage Combinations
V
PP
5 V, 12 V
VOLTAGE
PP
≤ V
CC
CC
, 12 V
PP
PPLK
and
CC
pin
PP
.
,