LH28F016LLT-12 Sharp Electronics, LH28F016LLT-12 Datasheet - Page 10

• Manufacturer Part Number: LH28F016LLT-12
• Manufacturer: Sharp Electronics

Specifications of LH28F016LLT-12

• Cell Type: NOR
• Density: 16Mb
• Access Time (max): 120ns
• Interface Type: Parallel
• Boot Type: Not Required
• Address Bus: 21/20Bit
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Package Type: TSOP-I
• Sync/async: Asynchronous
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 8/16Bit
• Number Of Words: 2M/1M
• Supply Current: 35mA
• Mounting: Surface Mount
• Pin Count: 56
• Lead Free Status / Rohs Status: Not Compliant

LH28F016LL
LH28F800SU Performance Enhancement Command Bus Definitions
ADDRESS
BA = Block Address
PA = Page Buffer Address
RA = Extended Register Address
WA = Write Address
X = Don’t Care
10
Read Extended
Status Register
Page Buffer Swap
Read Page Buffer
Single Load to
Page Buffer
Sequential Load to
Page Buffer
Page Buffer Write
to Flash
Two-Byte Write
Block
Erase/Confirm
Lock Block/Confirm
Upload Status
Bits/Confirm
Upload Device
Information
Erase All Unlocked
Blocks/Confirm
RY
Level-Mode
RY
Write
RY
Erase
RY
Sleep
Abort
»
/ BY
»
/ BY
»
/ BY
»
/ BY
COMMAND
»
»
»
»
Enable to
Pulse-On-
Pulse-On-
Disable
MODE
x16
x16
x8
x8
x8
OPER. ADDR.
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
FIRST BUS CYCLE
WC (L, H) = Word Count (Low, High)
DATA
AD = Array Data
PD = Page Buffer Data
BSRD = BSR Data
GSRD = GSR Data
BC (L, H) = Byte Count (Low, High)
WD (L, H) = Write Data (Low, High)
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
DATA
0CH
0CH
FBH
E0H
E0H
A7H
F0H
71H
72H
75H
74H
20H
77H
97H
99H
96H
96H
96H
96H
80H
OPER. ADDR.
SECOND BUS CYCLE
Read
Read
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
RA
PA
PA
BA
BA
A0
A0
X
X
X
X
X
X
X
X
X
X
GSRD
BSRD
DATA
(L, H)
(L, H)
WCL
WCL
BCL
D0H
D0H
D0H
D0H
D0H
01H
02H
03H
04H
WD
PD
BC
PD
16M (1M × 16, 2M × 8) Flash Memory
OPER. ADDR.
Write
Write
Write
Write
Write
Write
THIRD BUS CYCLE
WA
WA
WA
X
X
X
BC (H, L)
WD (H, L)
DATA
WCH
WCH
BCH
D0H
4, 6, 10
4, 5, 10
NOTE
6, 10
9, 10
4, 5,
3, 4,
11
1
7
3
2
8
8
8
8