LH28F016LLT-12 Sharp Electronics, LH28F016LLT-12 Datasheet - Page 11

• Manufacturer Part Number: LH28F016LLT-12
• Manufacturer: Sharp Electronics

Specifications of LH28F016LLT-12

• Cell Type: NOR
• Density: 16Mb
• Access Time (max): 120ns
• Interface Type: Parallel
• Boot Type: Not Required
• Address Bus: 21/20Bit
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Package Type: TSOP-I
• Sync/async: Asynchronous
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 8/16Bit
• Number Of Words: 2M/1M
• Supply Current: 35mA
• Mounting: Surface Mount
• Pin Count: 56
• Lead Free Status / Rohs Status: Not Compliant

16M (1M × 16, 2M × 8) Flash Memory
NOTES:
1. RA can be the GSR address or any BSR address. See Figure 4.1 and 4.2 for Extended Status Register Memory Maps.
2. Upon device power-up, all BSR lock-bits come up locked. The Uploaded Status Bits command must be written to reflect the actual
3. A
4. BCH/WCH must be at 00H for this product because of the 256-Byte (128 Word) Page Buffer size and to avoid writing the Page Buffer
5. In x16 mode, only the lower byte DQ
6. PA and PD (Whose count is given in cycles 2 and 3) are supplied starting in the 4th cycle which is not shown.
7. This command allows the user to swap between available Page Buffers (0 or 1).
8. These commands reconfigure RY
9. Write address, WA, is the Destination address in the flash array which must match the Source address in the Page Buffer. Refer to the
10. BCL = 00H corresponds to a Byte count of 1. Similarly, WCL = 00H corresponds to a Word count of 1.
11. Unless you issue erase suspend command, it is not necessary to input D0H on third bus cycle.
Compatible Status Register
CSR.7 = WRITE STATE MACHINE STATUS (WSMS)
CSR.6 = ERASE-SUSPEND STATUS (ESS)
CSR.5 = ERASE STATUS (ES)
CSR.4 = DATA-WRITE STATUS (DWS)
CSR.3 = V
lock-bit status.
first: A
contents into more than one 256-Byte segment within an array block. They are simply shown for future Page Buffer expandability.
LH28F016SU User’s Manual.
WSMS
0
is automatically complemented to load second byte of data. BY
7
0
= 0 looks at the WDL/BCL, A
1 = Ready
0 = Busy
1 = Erase Suspended
0 = Erase in Progress/Completed
1 = Error in Block Erasure
0 = Successful Block Erase
1 = Error in Data Write
0 = Data Write Successful
1 = V
0 = V
PP
STATUS (VPPS)
PP
PP
Low Detect, Operation Abort
OK
ESS
6
»
/ BY
0
0
»
ES
- DQ
output to one of two pulse-modes or enable and disable the RY
= 1 looks at the WDH/BCH.
5
7
is used for WCL and WCH. The upper byte DQ
DWS
4
»
T E
NOTES:
1. RY
2. If DWS and ES are set to ‘1’ during an erase attempt, an
3. The VPPS bit, unlike an A/D converter, does not provide
4. CSR.2 - CSR.0 = Reserved for future enhancements.
»
must be at V
VPPS
completion of an operation (Erase Suspend, Erase or Data
Write) before the appropriate Status bit (ESS, ES or DWS)
is checked for success.
improper command sequence was entered. Clear the CSR
and attempt the operation again.
continuous indication of V
V
sequences have been entered, and informs the system if
V
report accurate feedback between V
These bits are reserved for future use and should be
masked out when polling the CSR.
3
PP
PP
»
/ BY
’s level only after the Data-Write or Erase command
has not been switched on. VPPS is not guaranteed to
»
output or WSMS bit must be checked to determine
IL
. A
0
value determines which WD/BC is supplied
R
2
8
- DQ
15
PP
is a don’t care.
level. The WSM interrogates
»
/ BY
»
function.
R
1
PPL
and V
PPH
LH28F016LL
.
R
0
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