LH28F016LLT-12 Sharp Electronics, LH28F016LLT-12 Datasheet - Page 6

• Manufacturer Part Number: LH28F016LLT-12
• Manufacturer: Sharp Electronics

Specifications of LH28F016LLT-12

• Cell Type: NOR
• Density: 16Mb
• Access Time (max): 120ns
• Interface Type: Parallel
• Boot Type: Not Required
• Address Bus: 21/20Bit
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Package Type: TSOP-I
• Sync/async: Asynchronous
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 8/16Bit
• Number Of Words: 2M/1M
• Supply Current: 35mA
• Mounting: Surface Mount
• Pin Count: 56
• Lead Free Status / Rohs Status: Not Compliant

LH28F016LL
Registers to accomplish various functions:
•
•
•
Word-Wide modes are shown in Figures 4 and 5.
RY
tie many RY
figuration such as a Resident Flash Array.
enable function with two input pins, CE
pins have exactly the same functionality as the regulary
chip-enable pin CE
chip designs, CE
as the chip enable input. The LH28F016LL uses the logi-
cal combination of these two signals to enable or dis-
able the entire chip. Both CE
low to enable the device and if either one becomes in-
active, the chip will be disabled. This feature, along with
the open drain RY
to reduce the number of control pins used in a large
array of 16M devices.
the LH28F016LL. BY
with address A
byte. On the other hand, BY
16-bit operation with address A
order address and address A
A device diagram is shown in Figure 1.
time (t
and in operating temperature 0°C to +70°C.
Saving (APS) feature which substantially reduces the
active current when the device is in static mode of
operation (address not switching).
when the RP
transitions low. This mode brings the device power con-
sumption to less than 5 µA typically, and provides addi-
tional write protection by acting as a device reset pin
during power transitions. A reset time of 480 ns is re-
quired from RP
valid. In the Deep Power-Down state, the WSM is reset
6
The LH28F016LL contains three types of Status
A Compatible Status Register (CSR) which is 100%
compatible with the LH28F008SA Flash memory’s
Status Register. This register, when used alone, pro-
vides a straightforward upgrade capability to the
LH28F016LL from a LH28F008SA-based design.
A Global Status Register (GSR) which informs
the system of command Queue status. Page
Buffer status, and overall Write Status Machine
(WSM) status.
32 Block Status Registers (BSRs) which provide
block-specific status information such as the block
lock-bit status.
The GSR and BSR memory maps for Byte-Wide and
The LH28F016LL incorporates an open drain
The LH28F016LL also incorporates a dual chip-
The BY
The LH28F016LL is specified for a maximum access
The LH28F016LL incorporates an Automatic Power
In APS mode, the typical I
A Deep Power-Down mode of operation is invoked
»
/ BY
ACC
»
output pin. This feature allows the user to OR-
»
)150 ns, in operating voltage 2.7 V to 3.6 V
T E
»
/ BY
»
»
pin allows either x8 or x16 read/writes to
(called PWD on the LH28F008SA) pin
0
»
»
pins together in a multiple memory con-
switching high until outputs are again
»
selecting between low byte and high
1
»
/ BY
may be tied to ground and use CE
»
on the LH28F008SA. For minimum
»
T E
»
pin, allows the system designer
»
at logic low selects 8-bit mode
CC
»
0
»
T E
0
and CE
is not used (don’t care).
current is 1 mA at 3.0 V.
1
»
at logic high enables
becoming the lowest
»
0
»
1
and CE
must be active
»
1
. These
»
0
MEMORY MAP
(any current operation will abort) and the CSR, GSR
and BSR registers are cleared.
either CE
with all input control pins at CMOS levels. In this mode,
the device typically draws an I
10 µA.
A CMOS Standby mode of operation is enabled when
1EFFFFH
1DFFFFH
1CFFFFH
1BFFFFH
1AFFFFH
0EFFFFH
0DFFFFH
0CFFFFH
0BFFFFH
0AFFFFH
1FFFFFH
19FFFFH
18FFFFH
17FFFFH
16FFFFH
15FFFFH
14FFFFH
13FFFFH
12FFFFH
11FFFFH
10FFFFH
0FFFFFH
09FFFFH
08FFFFH
07FFFFH
06FFFFH
05FFFFH
04FFFFH
03FFFFH
02FFFFH
01FFFFH
00FFFFH
1E0000H
1D0000H
1C0000H
1B0000H
1A0000H
0E0000H
0D0000H
0C0000H
0B0000H
0A0000H
1F0000H
0F0000H
190000H
180000H
170000H
160000H
150000H
140000H
130000H
120000H
110000H
100000H
090000H
080000H
070000H
060000H
050000H
040000H
030000H
020000H
010000H
000000H
Figure 3. LH28F016LL Memory Map
»
0
or CE
16M (1M × 16, 2M × 8) Flash Memory
»
1
transitions high and RP
64KB BLOCK
64KB BLOCK
64KB BLOCK
64KB BLOCK
64KB BLOCK
64KB BLOCK
64KB BLOCK
64KB BLOCK
64KB BLOCK
64KB BLOCK
64KB BLOCK
64KB BLOCK
64KB BLOCK
64KB BLOCK
64KB BLOCK
64KB BLOCK
64KB BLOCK
64KB BLOCK
64KB BLOCK
64KB BLOCK
64KB BLOCK
64KB BLOCK
64KB BLOCK
64KB BLOCK
64KB BLOCK
64KB BLOCK
64KB BLOCK
64KB BLOCK
64KB BLOCK
64KB BLOCK
64KB BLOCK
64KB BLOCK
CC
standby current of
»
stays high
30
29
28
27
26
25
24
23
22
20
19
18
17
16
15
14
13
12
11
10
31
21
9
8
7
6
5
4
3
2
0
1
28F016LLT-3