TB28F008S3-150 Intel, TB28F008S3-150 Datasheet - Page 16

• Manufacturer Part Number: TB28F008S3-150
• Manufacturer: Intel

Specifications of TB28F008S3-150

• Density: 8Mb
• Access Time (max): 150ns
• Interface Type: Parallel
• Boot Type: Not Required
• Address Bus: 20b
• Operating Supply Voltage (typ): 3/3.3V
• Operating Temp Range: -40C to 85C
• Package Type: SOP
• Program/erase Volt (typ): 2.7 to 3.6V
• Sync/async: Asynchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 8b
• Number Of Words: 1M
• Supply Current: 18mA
• Mounting: Surface Mount
• Pin Count: 44
• Lead Free Status / Rohs Status: Not Compliant

28F004S3/28F008S3/28F016S3
4.1
Upon initial device power-up and after exit from
deep power-down mode, the device defaults to read
array mode. This operation is also initiated by
writing the Read Array command. The device
remains enabled for reads until another command
is written. Once the internal WSM has started a
block erase, program, or lock-bit configuration, the
device will not recognize the Read Array command
until the WSM completes its operation unless the
WSM is suspended via an Erase Suspend or
Program Suspend command. The Read Array
command functions independently of the V
voltage and RP# can be V
4.2
The identifier code operation is initiated by writing
the Read Identifier Codes command. Following the
command write, read cycles from addresses shown
in Figure 6 retrieve the manufacturer, device, block
lock configuration and master lock configuration
codes (see Table 4 for identifier code values). To
terminate
command. Like the Read Array command, the
Read
independently of the V
V
command, the subsequent information can be read.
NOTE:
1.
16
Manufacturer Code
Device Code
Block Lock Configuration
Master Lock Configuration
IH
Block Is Unlocked
Block Is Locked
Reserved for Future Use
Device Is Unlocked
Device Is Locked
Reserved for Future Use
X selects the specific block lock configuration code to
be read. See Figure 5 for the device identifier code
memory map.
or V
Identifier
HH
Read Array Command
Read Identifier Codes
Command
. Following the Read Identifier Codes
the
Code
Table 4. Identifier Codes
operation,
Codes
16-Mbit
4-Mbit
8-Mbit
PP
IH
voltage and RP# can be
or V
write
command
XX
Address
000000
000001
000001
000001
000003
HH
0002
.
another
(1)
DQ
DQ
DQ
DQ
functions
DQ
DQ
Data
AA
A7
A6
89
0
0
0
0
1–7
1–7
valid
= 0
= 1
= 0
= 1
PP
4.3
The status register may be read to determine when
a block erase, program, or lock-bit configuration is
complete and whether the operation completed
successfully. It may be read at any time by writing
the Read Status Register command. After writing
this command, all subsequent read operations
output data from the status register until another
valid command is written. The status register
contents are latched on the falling edge of OE# or
CE#, whichever occurs first. OE# or CE# must
toggle to V
Read
independently of the V
or V
4.4
Status register bits SR.5, SR.4, SR.3, and SR.1 are
set to “1”s by the WSM and can only be reset by
the Clear Status Register command. These bits
indicate various failure conditions (see Table 6). By
allowing system software to reset these bits,
several operations (such as cumulatively erasing or
locking multiple blocks or writing several bytes in
sequence) may be performed. The status register
may be polled to determine if an error occurred
during the sequence.
To clear the status register, the Clear Status
Register command (50H) is written. It functions
independently of the applied V
be V
during block erase or program suspend modes.
4.5
Erase is executed one block at a time and initiated
by a two-cycle command. A block erase setup is
written first, followed by a block erase confirm. This
command
quencing and an address within the block to be
erased (erase changes all block data to FFH).
Block preconditioning, erase, and verify are handled
internally by the WSM (invisible to the system).
After the two-cycle block erase sequence is written,
the device automatically outputs status register
data when read (see Figure 7). The CPU can detect
block erase completion by analyzing the RY/BY#
pin or status register bit SR.7.
HH
IH
.
Status
or V
Read Status Register
Command
Clear Status Register
Command
Block Erase Command
IH
sequence
to update the status register latch. The
HH
. This command is not functional
Register
PP
requires
PRELIMINARY
voltage. RP# can be V
command
PP
voltage. RP# can
appropriate
functions
se-
IH