TB28F008S3-150 Intel, TB28F008S3-150 Datasheet - Page 19

• Manufacturer Part Number: TB28F008S3-150
• Manufacturer: Intel

Specifications of TB28F008S3-150

• Density: 8Mb
• Access Time (max): 150ns
• Interface Type: Parallel
• Boot Type: Not Required
• Address Bus: 20b
• Operating Supply Voltage (typ): 3/3.3V
• Operating Temp Range: -40C to 85C
• Package Type: SOP
• Program/erase Volt (typ): 2.7 to 3.6V
• Sync/async: Asynchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 8b
• Number Of Words: 1M
• Supply Current: 18mA
• Mounting: Surface Mount
• Pin Count: 44
• Lead Free Status / Rohs Status: Not Compliant

4.10
All set block lock-bits are cleared in parallel via the
Clear Block Lock-Bits command. With the master
lock-bit not set, block lock-bits can be cleared using
only the Clear Block Lock-Bits command. If the
master lock-bit is set, clearing block lock-bits
requires both the Clear Block Lock-Bits command
and V
summary of hardware and software write protection
options.
Clear block lock-bits operation is initiated using a
two-cycle command sequence. A clear block
lock-bits setup is written first. Then, the device
automatically outputs status register data when
read (see Figure 12). The CPU can detect
completion of the clear block lock-bits event by
analyzing the RY/BY# pin output or status register
bit SR.7.
When the operation is complete, status register bit
SR.5 should be checked. If a clear block lock-bit
error is detected, the status register should be
cleared. The CUI will remain in read status register
mode until another command is issued.
Block Erase or
Byte Write
Set Block
Lock-Bit
Set Master
Lock-Bit
Clear Block
Lock-Bits
PRELIMINARY
Operation
HH
Clear Block Lock-Bits
Command
on the RP# pin. See Table 5 for a
Lock-Bit
Master
X
X
0
1
0
1
Lock-Bit
Block
0
1
X
X
X
X
X
Table 5. Write Protection Alternatives
V
V
V
IH
IH
IH
RP#
V
V
V
V
V
V
V
V
or V
or V
or V
HH
HH
HH
HH
IH
IH
IH
IH
HH
HH
HH
Block Erase and Program Enabled
Block is Locked. Block Erase and Program Disabled
Block Lock-Bit Override. Block Erase and Program
Enabled
Set Block Lock-Bit Enabled
Master Lock-Bit is Set. Set Block Lock-Bit Disabled
Master Lock-Bit Override. Set Block Lock-Bit
Enabled
Set Master Lock-Bit Disabled
Set Master Lock-Bit Enabled
Clear Block Lock-Bits Enabled
Master Lock-Bit is Set. Clear Block Lock-Bits
Disabled
Master Lock-Bit Override. Clear Block Lock-Bits
Enabled
This two-step sequence of set-up followed by
execution ensures that block lock-bits are not
accidentally
Lock-Bits command sequence will result in status
register bits SR.4 and SR.5 being set to “1.” Also, a
reliable clear block lock-bits operation can only
occur when V
clear block lock-bits operation is attempted while
V
absence of this high voltage, the block lock-bits
content are protected against alteration. A suc-
cessful clear block lock-bits operation requires that
the master lock-bit is not set or, if the master lock-
bit is set, that RP# = V
master lock-bit set and RP# = V
will be set to “1” and the operation will fail. A clear
block lock-bits operation with V
produce spurious results and should not be
attempted.
If a clear block lock-bits operation is aborted due to
V
active transition, block lock-bit values are left in an
undetermined state. A repeat of clear block lock-
bits is required to initialize block lock-bit contents to
known values. Once the master lock-bit is set, it
cannot be cleared.
PP
PP
or V
V
PPLK
CC
, SR.3 and SR.5 will be set to “1.” In the
transitioning out of valid range or RP#
cleared.
CC
28F004S3/28F008S3/28F016S3
= V
Effect
CC2
HH
An
. If it is attempted with the
and V
invalid
PP
IH
IH
, SR.1 and SR.5
= V
< RP# < V
Clear
PPH1/2
Block
. If a
19
HH