TB28F008S3-150 Intel, TB28F008S3-150 Datasheet - Page 7

• Manufacturer Part Number: TB28F008S3-150
• Manufacturer: Intel

Specifications of TB28F008S3-150

• Density: 8Mb
• Access Time (max): 150ns
• Interface Type: Parallel
• Boot Type: Not Required
• Address Bus: 20b
• Operating Supply Voltage (typ): 3/3.3V
• Operating Temp Range: -40C to 85C
• Package Type: SOP
• Program/erase Volt (typ): 2.7 to 3.6V
• Sync/async: Asynchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 8b
• Number Of Words: 1M
• Supply Current: 18mA
• Mounting: Surface Mount
• Pin Count: 44
• Lead Free Status / Rohs Status: Not Compliant

A
DQ
CE#
RP#
OE#
WE#
RY/BY#
V
V
GND
NC
0
PP
CC
PRELIMINARY
–A
Sym
0
–DQ
20
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OUTPUT
OUTPUT READY/BUSY#: Indicates the status of the internal WSM. When low, the WSM is
SUPPLY BLOCK ERASE, PROGRAM, LOCK-BIT CONFIGURATION POWER SUPPLY:
SUPPLY DEVICE POWER SUPPLY: Internal detection automatically configures the device
SUPPLY GROUND: Do not float any ground pins.
INPUT/
INPUT
INPUT
INPUT
INPUT
INPUT
Type
ADDRESS INPUTS: Inputs for addresses during read and write operations.
Addresses are internally latched during a write cycle.
DATA INPUT/OUTPUTS: Inputs data and commands during CUI write cycles;
outputs data during memory array, status register, and identifier code read cycles.
Data pins float to high-impedance when the chip is deselected or outputs are
disabled. Data is internally latched during a write cycle.
CHIP ENABLE: Activates the device’s control logic, input buffers, decoders, and
sense amplifiers. CE#-high deselects the device and reduces power consumption to
standby levels.
RESET/DEEP POWER-DOWN: When driven low, RP# inhibits write operations
which provides data protection during power transitions, puts the device in deep
power-down mode, and resets internal automation. RP#-high enables normal
operation. Exit from deep power-down sets the device to read array mode.
RP# at V
lock-bits when the master lock-bit is set. RP# = V
thereby enabling block erase and program operations to locked memory blocks.
Block erase, program, or lock-bit configuration with V
spurious results and should not be attempted.
OUTPUT ENABLE: Gates the device’s outputs during a read cycle.
WRITE ENABLE: Controls writes to the CUI and array blocks. Addresses and data
are latched on the rising edge of the WE# pulse.
performing an internal operation (block erase, program, or lock-bit). RY/BY#-high
indicates that the WSM is ready for new commands, block erase or program is
suspended, or the device is in deep power-down mode. RY/BY# is always active.
For erasing array blocks, programming data, or configuring lock-bits.
With V
lock-bit configuration with an invalid V
results and should not be attempted.
for optimized read performance. Do not float any power pins.
With V
operations at invalid V
results and should not be attempted. Block erase, program, and lock-bit
configuration operations with V
NO CONNECT: Lead is not internally connected; it may be driven or floated.
PP
CC
HH
V
V
16 Mbit
enables setting of the master lock-bit and enables configuration of block
3 Volt Flash
3 Volt Flash
PPLK
4 Mbit
8 Mbit
LKO
, all write attempts to the flash memory are inhibited. Device
Table 1. Pin Descriptions
, memory contents cannot be altered. Block erase, program, and
CC
A
A
A
0
voltages (see DC Characteristics ) produce spurious
0
0
–A
–A
–A
2.7 V, 3.3 V and 12 V V
2.7 V and 3.3 V V
18
19
20
CC
Name and Function
< 2.7 V are not supported.
PP
(see DC Characteristics ) produce spurious
CC
28F004S3/28F008S3/28F016S3
HH
overrides block lock-bits,
PP
IH
< RP# < V
HH
produce
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