CY7C131-25NC Cypress Semiconductor Corp, CY7C131-25NC Datasheet - Page 12

• Manufacturer Part Number: CY7C131-25NC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C131-25NC

• Density: 8Kb
• Access Time (max): 25ns
• Sync/async: Asynchronous
• Architecture: Not Required
• Clock Freq (max): Not RequiredMHz
• Operating Supply Voltage (typ): 5V
• Address Bus: 20b
• Package Type: PQFP
• Operating Temp Range: 0C to 70C
• Number Of Ports: 2
• Supply Current: 170mA
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 52
• Word Size: 8b
• Number Of Words: 1K
• Lead Free Status / Rohs Status: Not Compliant

Switching Waveforms
Document Number: 38-06002 Rev. *G
Notes
ADDRESS
36. The internal write time of the memory is defined by the overlap of CS LOW and R/W LOW. Both signals must be low to initiate a write and either signal can
37. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of t
38. These parameters are measured from the input signal changing, until the output pin goes to a high-impedance state.
39. If the CE LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the high impedance state.
ADDRESS
DATA
DATA
D
DATA
terminate a write by going high. The data input setup and hold timing should be referenced to the rising edge of the signal that terminates the write.
and for data to be placed on the bus for the required t
OUT
R/W
OE
CE
R/W
IN
OUT
CE
IN
Figure 9. Write Cycle No. 2 (R/W Three-States Data I/Os—Either Port)
Figure 8. Write Cycle No. 1 (OE Three-States Data I/Os—Either Port
t
HZOE
t
SA
(continued)
t
SA
SD
.
t
SCE
t
SCE
t
AW
t
AW
t
Either Port
HZWE
t
WC
t
WC
HIGH IMPEDANCE
t
PWE
DATA VALID
t
PWE
t
SD
PWE
HIGH IMPEDANCE
or t
t
DATA VALID
SD
HZWE
+ t
SD
to allow the data I/O pins to enter high impedance
t
HD
t
HD
t
LZWE
t
HA
t
HA
CY7C130, CY7C130A
CY7C131, CY7C131A
[36, 37]
[38, 39]
Page 12 of 22
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