TE28F160B3TA110 Intel, TE28F160B3TA110 Datasheet - Page 5

• Manufacturer Part Number: TE28F160B3TA110
• Manufacturer: Intel

Specifications of TE28F160B3TA110

• Cell Type: NOR
• Density: 16Mb
• Access Time (max): 110ns
• Interface Type: Parallel
• Boot Type: Top
• Address Bus: 20b
• Operating Supply Voltage (typ): 3/3.3V
• Operating Temp Range: -40C to 85C
• Package Type: TSOP
• Sync/async: Asynchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 16b
• Number Of Words: 1M
• Supply Current: 18mA
• Mounting: Surface Mount
• Pin Count: 48
• Lead Free Status / Rohs Status: Not Compliant

Revision History
Datasheet
Number
-001
-002
-003
-004
-005
-006
-007
Original version
Section 3.4, V
Updated Figure 9: Automated Block Erase Flowchart
Updated Figure 10: Erase Suspend/Resume Flowchart (added program to table)
Updated Figure 16: AC Waveform: Program and Erase Operations (updated notes)
I
Program and Erase Suspend Latency specification change
Updated Appendix A: Ordering Information (included 8 M and 4 M information)
Updated Figure, Appendix D: Architecture Block Diagram (Block info. in words not bytes)
Minor wording changes
Combined byte-wide specification (previously 290605) with this document
Improved speed specification to 80 ns (3.0 V) and 90 ns (2.7 V)
Improved 1.8 V I/O option to minimum 1.65 V (Section 3.4)
Improved several DC characteristics (Section 4.4)
Improved several AC characteristics (Sections 4.5 and 4.6)
Combined 2.7 V and 1.8 V DC characteristics (Section 4.4)
Added 5 V V
Removed 120 ns and 150 ns speed offerings
Moved Ordering Information from Appendix to Section 6.0; updated information
Moved Additional Information from Appendix to Section 7.0
Updated figure Appendix B, Access Time vs. Capacitive Load
Updated figure Appendix C, Architecture Block Diagram
Moved Program and Erase Flowcharts to Appendix E
Updated Program Flowchart
Updated Program Suspend/Resume Flowchart
Minor text edits throughout
Added 32-Mbit density
Added 98H as a reserved command (Table 4)
A
Status register clarification for SR3 (Table 7)
V
Combined I
Combined I
Max Parameter Block Erase Time (t
Max Main Block Erase Time (t
Erase suspend time @ 12 V (t
(Section 4.7)
Ordering Information updated (Section 6.0)
Write State Machine Current/Next States Table updated (Appendix A)
Program Suspend/Resume Flowchart updated (Appendix F)
Erase Suspend/Resume Flowchart updated (Appendix F)
Text clarifications throughout
I
32-Mbit ordering information corrected (Section 6)
V
I
Added Command Sequence Error Note (Table 7)
Data sheet renamed from Smart 3 Advanced Boot Block 4-Mbit, 8-Mbit, 16-Mbit Flash
Memory Family.
Added device ID information for 4-Mbit x8 device
Removed 32-Mbit x8 to reflect product offerings
Minor text changes
Corrected RP# pin description in Table 2, 3 Volt Advanced Boot Block Pin Descriptions
Corrected typographical error fixed in Ordering Information
PPR
PPD
CCS
BGA package diagrams corrected (Figures 3 and 4)
BGA package top side mark information added (Section 6)
1
CC
IH
–A
and V
and V
maximum specification change from ±25 A to ±50 A
test conditions corrected (Section 4.4)
test conditions clarification (Section 4.4)
20
= 0 when in read identifier mode (Section 3.2.2)
IL
CCQ
Specification change (Section 4.4)
PPW
PPE
PP
PP
absolute maximum specification = 3.7 V (Section 4.1)
read specification (Section 3.4)
and I
and I
Program and Erase Voltages, added
CCE
CCW
28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
into one specification (Section 4.4)
into one specification (Section 4.4)
WHQV3
WHRH2
WHQV2
/t
/t
EHQV3
EHRH2
Description
/t
EHQV2
) reduced to 5 sec (Section 4.7)
) changed to 5 µs typical and 20 µs maximum
) reduced to 4 sec (Section 4.7)
5