TE28F160B3TA110 Intel, TE28F160B3TA110 Datasheet - Page 55

• Manufacturer Part Number: TE28F160B3TA110
• Manufacturer: Intel

Specifications of TE28F160B3TA110

• Cell Type: NOR
• Density: 16Mb
• Access Time (max): 110ns
• Interface Type: Parallel
• Boot Type: Top
• Address Bus: 20b
• Operating Supply Voltage (typ): 3/3.3V
• Operating Temp Range: -40C to 85C
• Package Type: TSOP
• Sync/async: Asynchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 16b
• Number Of Words: 1M
• Supply Current: 18mA
• Mounting: Surface Mount
• Pin Count: 48
• Lead Free Status / Rohs Status: Not Compliant

11.0
11.1
Datasheet
00, 01,
60, 2F,
C0, 98
Code
Table 26. Command Codes and Descriptions (Sheet 1 of 2)
FF
D0
40
10
20
Program Set-Up
Program Set-Up
Program / Erase
Erase Confirm
Device Mode
Erase Set-Up
Read Array
Modes of Operation
The flash memory has four read modes (read array, read identifier, read status, and read query; see
Figure 1, “B3 Architecture Block Diagram” on page
erase). Three additional modes (erase suspend to program, erase suspend to read, and program
suspend to read) are available only during suspended operations.
Descriptions” on page 55
“Write State Machine Current/Next States,”
Read Array
When RP# transitions from V
respond to the read-control inputs (CE#, address inputs, and OE#) without any additional CUI
commands.
When the device is in read-array mode, four control signals control data output.
In addition, the address of the preferred location must be applied to the address pins. If the device is
not in read-array mode, as would be the case after a Program or Erase operation, the Read Array
command (FFH) must be written to the CUI before array reads can occur.
Reserved
Alternate
Resume
Invalid/
•
•
•
•
WE# must be logic high (V
CE# must be logic low (V
OE# must be logic low (V
RP# must be logic high (V
Unassigned commands that must not be used. Intel reserves the right to redefine these codes
for future functions.
Places the device in read-array mode, such that array data will be output on the data pins.
This is a two-cycle command. The first cycle prepares the CUI for a program operation. The
second cycle latches addresses and data information and initiates the WSM to execute the
program algorithm. The flash outputs Status Register data when CE# or OE# is toggled. A
Read Array command is required after programming to read array data. See
(See 40H/Program Set-Up)
Prepares the CUI for the Erase Confirm command. If the next command is not an Erase
Confirm command, then the CUI will (a) set both SR.4 and SR.5 of the Status Register to a “1,”
(b) place the device into the read-Status Register mode, and (c) wait for another command.
See
If the previous command was an Erase Set-Up command, then the CUI will close the address
and data latches, and begin erasing the block indicated on the address pins. During erase, the
device will only respond to the Read Status Register and Erase Suspend commands. The
device will output Status Register data when CE# or OE# is toggled.
If a Program or Erase operation was previously suspended, this command will resume that
operation.
Section 11.5, “Erase Mode” on page
summarizes the commands used to reach these modes.
IL
IL
IL
IH
IH
(reset) to V
)
)
)
)
28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
IH
is a comprehensive chart showing the state transitions.
, the device defaults to read-array mode and will
Description
58.
10), and two write modes (program and block
Table 26, “Command Codes and
Appendix A,
Section
11.4.
55