S29GL256M10TAIR10 Spansion Inc., S29GL256M10TAIR10 Datasheet - Page 74

• Manufacturer Part Number: S29GL256M10TAIR10
• Manufacturer: Spansion Inc.

Specifications of S29GL256M10TAIR10

• Cell Type: NOR
• Density: 256Mb
• Access Time (max): 100ns
• Interface Type: Parallel
• Boot Type: Not Required
• Address Bus: 25/24Bit
• Operating Supply Voltage (typ): 3/3.3V
• Operating Temp Range: -40C to 85C
• Package Type: TSOP
• Program/erase Volt (typ): 3/11.5 to 12.5V
• Sync/async: Asynchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 8/16Bit
• Number Of Words: 32M/16M
• Supply Current: 60mA
• Mounting: Surface Mount
• Pin Count: 56
• Lead Free Status / Rohs Status: Not Compliant

RY/BY#: Ready/Busy#
DQ6: Toggle Bit I
72
Notes:
1.
2.
The RY/BY# is a dedicated, open-drain output pin which indicates whether an Embedded Algo-
rithm is in progress or complete. The RY/BY# status is valid after the rising edge of the final WE#
pulse in the command sequence. Since RY/BY# is an open-drain output, several RY/BY# pins can
be tied together in parallel with a pull-up resistor to V
If the output is low (Busy), the device is actively erasing or programming. (This includes program-
ming in the Erase Suspend mode.) If the output is high (Ready), the device is in the read mode,
the standby mode, or in the erase-suspend-read mode.
Toggle Bit I on DQ6 indicates whether an Embedded Program or Erase algorithm is in progress or
complete, or whether the device entered the Erase Suspend mode. Toggle Bit I may be read at
any address, and is valid after the rising edge of the final WE# pulse in the command sequence
(prior to the program or erase operation), and during the sector erase time-out.
During an Embedded Program or Erase algorithm operation, successive read cycles to any ad-
dress cause DQ6 to toggle. The system may use either OE# or CE# to control the read cycles.
When the operation is complete, DQ6 stops toggling.
VA = Valid address for programming. During a sector erase operation, a valid address is any
sector address within the sector being erased. During chip erase, a valid address is any
non-protected sector address.
DQ7 should be rechecked even if DQ5 = “1” because DQ7 can change simultaneously with DQ5.
No
Figure 7. Data# Polling Algorithm
S29GL-M MirrorBit
Read DQ15–DQ0
Read DQ15–DQ0
DQ7 = Data?
DQ7 = Data?
Addr = VA
Addr = VA
DQ5 = 1?
START
FAIL
No
Yes
No
D a t a
TM
Yes
Yes
Flash Family
S h e e t
PASS
CC
Table 36
.
shows the outputs for RY/BY#.
S29GL-M_00_B8 February 7, 2007