PSB4860HV4.1 Lantiq, PSB4860HV4.1 Datasheet - Page 128

• Manufacturer Part Number: PSB4860HV4.1
• Manufacturer: Lantiq

Specifications of PSB4860HV4.1

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Data Sheet
Table 97
1M x4
4M x4 (2k refresh)
4M x4 (4k refresh)
2M x8
16M x4 (4k refresh)
16M x4 (8k refresh)
8M x8 (4k refresh)
8M x8 (8k refresh)
1)
The timing of the ARAM/DRAM interface is shown in figures 66 to 68. The timing is
derived from the internal memory clock MCLK which runs at a quarter of the system
clock.
Figure 66 ARAM/DRAM Interface - Read Cycle Timing
see chip control register CCTL
CAS
MA
MD
Address Line Usage (ARAM/DRAM Mode)
0
0
,CAS
0
MCLK
-MA
-MD
RAS
13
1
7
row addr.
0
0
0
0
0
0
0
0
A
A
A
A
A
A
A
A
128
0
0
0
0
0
0
0
0
-A
-A
-A
-A
-A
-A
-A
-A
8
8
8
8
8
8
8
8
col. addr.
A
A
A
A
A
A
A
A
9
9
9
9
9
9
9
9
A
A
A
A
A
A
A
10
10
10
10
10
10
10
A
11
A
A
A
A
11
11
11
11
PSB 4860
2000-01-14
A
A
12
12