PSB4860HV4.1 Lantiq, PSB4860HV4.1 Datasheet - Page 129

• Manufacturer Part Number: PSB4860HV4.1
• Manufacturer: Lantiq

Specifications of PSB4860HV4.1

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Figure 67 ARAM/DRAM Interface - Write Cycle Timing
Figure 68 ARAM/DRAM Interface - Refresh Cycle Timing
The
successive accesses.
The frequency at which refresh cycles are performed is shown in table 98.
Table 98
1)
Data Sheet
Refresh frequency
64 kHz
8, 16, 32 or 64 kHz
as programmed by HWCONFIG2:RSEL
ensures that RAS remains inactive for at least one MCLK-cycle between
CAS
CAS
MA
MD
Refresh Frequency Selection
0
0
0
MCLK
,CAS
0
MCLK
,CAS
-MA
-MD
RAS
RAS
W
13
1
7
1
1)
Comment
Memory access (e.g. recording) in progress
No memory access in progress or power-down
row addr.
129
data out
col. addr.
PSB 4860
2000-01-14