TDA6500TT NXP Semiconductors, TDA6500TT Datasheet - Page 6

• Manufacturer Part Number: TDA6500TT
• Manufacturer: NXP Semiconductors

Specifications of TDA6500TT

• Pin Count: 32
• Screening Level: Commercial
• Package Type: TSSOP
• Lead Free Status / Rohs Status: Compliant

Philips Semiconductors
9397 750 15057
Product data sheet
7.2.1 Write mode
7.2 Device control
Table 4:
The AGC detector provides information about the IF amplifier level. Five AGC take-over
points are available by software. Two programmable AGC time constants are available for
search tuning and normal tuner operation. The synthesizer consists of a 15-bit
programmable divider, a crystal oscillator and its programmable reference divider and a
phase/frequency detector combined with a charge pump, which drives the tuning amplifier
including 33 V output.
Depending on the reference divider ratio (64, 80 or 128) the phase comparator operates
at 62.50 kHz, 50.00 kHz or 31.25 kHz with a 4 MHz crystal.
The device can be controlled according to the I
set to logic 1 when the loop is locked. The AGC bit is set to logic 1 when the internal AGC
is active (level below 3 V). These two flags are read on the SDA line (status byte) during a
read operation (see
The ADC input is available on pin P6/ADC for digital AFC control. The ADC code is read
during a read operation (see
for
A minimum of seven bytes, including address byte, is required to address the device,
select the VCO frequency, program the ports, set the charge pump current, set the
reference divider ratio, select the AGC take-over point and select the AGC time constant.
The device has four independent I
specific voltage on input AS (see
The device is controlled via the I
the R/W bit for selecting the read or the write mode is required.
Data bytes can be sent to the device after the address transmission (first byte). Seven
data bytes are needed to fully program the device. The bus transceiver has an
auto-increment facility, which permits the programming of the device within one single
transmission (address + 6 data bytes).
The device can also be partially programmed providing that the first data byte following
the address is the first divider byte DB1 or the control byte CB. The data bytes are defined
in
The first bit of the first data byte indicates whether frequency data (first bit = 0) or control,
port and auxiliary data (first bit = 1) will follow. Until an I
the controller, additional data bytes can be entered without the need to re-address the
device. The frequency register is loaded with data from byte DB2 after the 8th SCL clock
Bit
P0
1
0
0
Table 5
1
2
f
ref
and
and
Mixer and oscillator band selection
P1
0
1
0
1
2
Table
f
div
(see
5 V mixer/oscillator and synthesizer for PAL and NTSC standards
Table
6.
Rev. 02 — 14 June 2005
Table
Mixer band
low
x
11).
Table
8).
2
C-bus. For programming, a module address of 7 bits and
Table
2
11). In test mode, pin P6/ADC is used as a test output
C-bus addresses which can be selected by applying a
mid
x
x
7).
2
high
x
x
C-bus format. The lock detector bit FL is
TDA6500; TDA6501
2
C-bus STOP command is sent by
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Oscillator band
low
x
mid
x
high
x
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