TDA6500TT NXP Semiconductors, TDA6500TT Datasheet - Page 7

• Manufacturer Part Number: TDA6500TT
• Manufacturer: NXP Semiconductors

Specifications of TDA6500TT

• Pin Count: 32
• Screening Level: Commercial
• Package Type: TSSOP
• Lead Free Status / Rohs Status: Compliant

Philips Semiconductors
9397 750 15057
Product data sheet
pulse, the control register is loaded with data from byte CB after the 8th SCL clock pulse,
the band switch register is loaded with data of byte BB after the 8th SCL clock pulse and
the auxiliary register is loaded with data of byte AB after the 8th SCL clock pulse.
To program the AGC take-over point setting and the AGC current to a different value than
the default value, an additional byte, the auxiliary byte, has to be sent. To this end, the
auxiliary byte is preceded by a control byte with the test bits T2, T1 and T0 set to logic 011
(see
Table 5:
[1]
Table 6:
Name
Address byte
Divider byte 1
Divider byte 2
Control byte
Band switch byte BB
Auxiliary byte
Symbol
A
MA1 and MA0
R/W
N14 to N0
CP
T2, T1 and T0
RSA and RSB
OS
P6 and P4
P3 to P0
ATC
AL2, AL1 and AL0
Auxiliary byte AB replaces band switch byte BB when bit T2 = 0, T1 = 1 and T0 = 1.
Table
I
Description of bits shown in
8).
2
C-bus data format for write mode
[1]
Byte
ADB
DB1
DB2
CB
AB
5 V mixer/oscillator and synthesizer for PAL and NTSC standards
Description
acknowledge
programmable address bits; see
logic 0 for write mode
programmable divider bits;
N = (N14
charge pump current
test bits; see
reference divider ratio select bits; see
tuning amplifier control bit
NPN port control bits
PMOS port control bits
AGC time constant
AGC take-over point bits; see
CP = 0: the charge pump current is 60 A
CP = 1: the charge pump current is 280 A (default)
OS = 0: normal operation; tuning voltage is on
OS = 1: tuning voltage is off; high-impedance state (default)
Pn = 0: port n is off; high-impedance state (default)
Pn = 1: buffer n is on; V
Pn = 0: port n is off; high-impedance state (default)
Pn = 1: buffer n is on; V
ATC = 0: I
ATC = 1: I
Rev. 02 — 14 June 2005
Bit
MSB
1
0
N7
1
0
ATC
2
AGC
AGC
1
N14
N6
CP
P6
AL2
14
Table 8
) + (N13
= 220 nA; t = 2 s with C = 160 nF (default)
= 9 A; t = 50 ms with C = 160 nF
Table 5
0
N13
N5
T2
0
AL1
2
O
O
13
= V
= V
0
N12
N4
T1
P4
AL0
) + ... + (N1
Table 10
TDA6500; TDA6501
CE(sat)
CC
Table 7
0
N11
N3
T0
P3
0
V
DS(sat)
Table 9
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
2
MA1
N10
N2
RSA
P2
0
1
) + N0
MA0
N9
N1
RSB
P1
0
LSB
R/W = 0 A
N8
N0
OS
P0
0
Ack
A
A
A
A
A
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