UDA1384H NXP Semiconductors, UDA1384H Datasheet - Page 26

• Manufacturer Part Number: UDA1384H
• Description: Encoders, Decoders, Multiplexers & Demultiplexers LO CST MULTICH CODEC
• Manufacturer: NXP Semiconductors

Specifications of UDA1384H

• Maximum Operating Temperature: + 85 C
• Package / Case: SOT-307
• Minimum Operating Temperature: - 20 C
• Mounting Style: SMD/SMT
• Lead Free Status / Rohs Status: Details
• Other names: UDA1384H/N1,557

Table 21:
[1]
[2]
Add
19h
1Ah
1Bh
1Ch
1Dh
ADC input amplifier gain settings
20h
21h
Supplemental settings
30h
31h
When writing new settings via the L3-bus interface, the default values should always be set to warrant correct operation. Read access to the DAC features register 11h will not
return valid data.
When bit RST is set to logic 1, the default values are set to all the registers as shown in
mute control bits MTA, MTB, MTV, MT and QM are set to logic 1. All other registers have non fixed values.
Function
DAC mixing
channel 2
DAC mixing
channel 3
DAC mixing
channel 4
DAC mixing
channel 5
DAC mixing
channel 6
ADC 1 and ADC 2
input amplifier gain
voice ADC input
amplifier gain
supplemental
settings 1
supplemental
settings 2
UDA1384 register mapping
D15
-
0
ICS1
0
-
0
ICS1
0
-
0
-
0
-
-
-
0
-
0
D14
-
0
ICS0
0
-
0
ICS0
0
-
0
-
0
-
-
-
0
-
0
[1]
…continued
D13
-
0
-
0
-
0
-
0
-
0
-
0
-
-
-
0
-
0
D12
-
0
-
0
-
0
-
0
-
0
-
0
-
-
-
0
-
0
IB3
0
-
-
-
0
-
0
D11
-
0
-
0
-
0
-
0
-
0
D10
PD
0
PD
0
PD
0
PD
0
PD
0
IB2
0
-
-
-
0
-
0
D9
MT
0
MT
0
MT
0
MT
0
MT
0
IB1
0
-
-
-
0
-
0
Table
21. When start-up, all the registers in 00h are initialized as the default values and the
D8
QM
0
QM
0
QM
0
QM
0
QM
0
IB0
0
-
-
-
0
-
0
D7
VC7
0
VC7
0
VC7
0
VC7
0
VC7
0
-
0
-
0
PDT
0
-
0
D6
VC6
0
VC6
0
VC6
0
VC6
0
VC6
0
-
0
-
0
-
0
DITH2 DITH1 DITH0 -
0
D5
VC5
0
VC5
0
VC5
0
VC5
0
VC5
0
-
0
-
0
-
0
0
D4
VC4
0
VC4
0
VC4
0
VC4
0
VC4
0
-
0
IV4
0
-
0
0
D3
VC3
0
VC3
0
VC3
0
VC3
0
VC3
0
IA3
0
IV3
0
-
0
0
D2
VC2
0
VC2
0
VC2
0
VC2
0
VC2
0
IA2
0
IV2
0
-
0
-
0
D1
VC1
0
VC1
0
VC1
0
VC1
0
VC1
0
IA1
0
IV1
0
-
0
VMTP PDLNA
0
D0
VC0
0
VC0
0
VC0
0
VC0
0
VC0
0
IA0
0
IV0
0
-
0
0