GAL20XV10B-15LP Lattice, GAL20XV10B-15LP Datasheet

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GAL20XV10B-15LP

Manufacturer Part Number
GAL20XV10B-15LP
Description
SPLD GAL Family 10 Macro Cells 83.3MHz EECMOS Technology 5V 24-Pin PDIP
Manufacturer
Lattice
Datasheet

Specifications of GAL20XV10B-15LP

Package
24PDIP
Family Name
GAL
Number Of Macro Cells
10
Maximum Propagation Delay Time
15 ns
Typical Operating Supply Voltage
5 V
Maximum Internal Frequency
83.3 MHz
Number Of Product Terms Per Macro
4
Re-programmability Support
Yes

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• HIGH PERFORMANCE E
• 50% to 75% REDUCTION IN POWER FROM BIPOLAR
• ACTIVE PULL-UPS ON ALL PINS
• E
• TEN OUTPUT LOGIC MACROCELLS
• PRELOAD AND POWER-ON RESET OF ALL REGISTERS
• APPLICATIONS INCLUDE:
• ELECTRONIC SIGNATURE FOR IDENTIFICATION
Copyright © 1997 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
20xv10_02
The GAL20XV10 combines a high performance CMOS process
with electrically erasable (E
the highest speed Exclusive-OR PLD available in the market. At
90mA maximum Icc (75mA typical Icc), the GAL20XV10 provides
a substantial savings in power when compared to bipolar counter-
parts. E
times providing the ability to reprogram, reconfigure or test the de-
vices quickly and efficiently.
The generic architecture provides maximum design flexibility by
allowing the Output Logic Macrocell (OLMC) to be configured by
the user. An important subset of the many architecture configu-
rations possible with the GAL20XV10 are the PAL
listed in the macrocell description section of this document. The
GAL20XV10 is capable of emulating these PAL architectures with
full function and parametric compatibility.
Unique test circuitry and reprogrammable cells allow complete AC,
DC, and functional testing during manufacturing. As a result, Lattice
Semiconductor delivers 100% field programmability and function-
ality of all GAL products. In addition, 100 erase/write cycles and
data retention in excess of 20 years are specified.
Features
Description
— 10 ns Maximum Propagation Delay
— Fmax = 100 MHz
— 7 ns Maximum from Clock Input to Data Output
— TTL Compatible 16 mA Outputs
— UltraMOS
— 90mA Maximum Icc
— 75mA Typical Icc
— Reconfigurable Logic
— Reprogrammable Cells
— 100% Tested/100% Yields
— High Speed Electrical Erasure (<100 ms)
— 20 Year Data Retention
— XOR Gate Capability on all Outputs
— Full Function and Parametric Compatibility with
— Registered or Combinatorial with Polarity
— High Speed Counters
— Graphics Processing
— Comparators
2
CELL TECHNOLOGY
PAL12L10, 20L10, 20X10, 20X8, 20X4
2
CMOS technology offers high speed (<100ms) erase
®
Advanced CMOS Technology
2
2
) floating gate technology to provide
CMOS
®
TECHNOLOGY
®
architectures
1
Functional Block Diagram
Pin Configuration
NC
I
I
I
I
I
I
11
5
7
9
12
4
GAL20XV10
I/CLK
I/OE
Top View
PLCC
I
I
I
I
I
I
I
I
I
I
14
2
28
16
26
18
21
23
25
19
I/O/Q
I/O/Q
I/O/Q
NC
I/O/Q
I/O/Q
I/O/Q
High-Speed E
GAL20XV10
Generic Array Logic™
I/CLK
GND
4
4
4
4
4
4
4
4
4
4
I
I
I
I
I
I
I
I
I
I
OLMC
OLMC
OLMC
OLMC
OLMC
OLMC
OLMC
OLMC
OLMC
OLMC
1
6
12
20XV10
2
GAL
DIP
CMOS PLD
July 1997
18
24
13
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
Vcc
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/OE
I/O/Q
I/O/Q
I/O/Q

Related parts for GAL20XV10B-15LP

GAL20XV10B-15LP Summary of contents

Page 1

... GAL products. In addition, 100 erase/write cycles and data retention in excess of 20 years are specified. Copyright © 1997 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. ...

Page 2

... GAL20XV10 Ordering Information Commercial Grade Specifications Part Number Description GAL20XV10B Device Name Speed (ns Low Power Power Specifications GAL20XV10 ( XXXXXXXX Grade Blank = Commercial Package P = Plastic DIP J = PLCC ...

Page 3

Output Logic Macrocell (OLMC) The following discussion pertains to configuring the Output Logic Macrocell. It should be noted that actual implementation is accomplished by development software/hardware and is com- pletely transparent to the user. The GAL20XV10 has two global architecture ...

Page 4

Input Mode OE CLK XOR CLK OE XOR Specifications GAL20XV10 XOR Registered Configuration - SYN = 1. - AC0 = 0. - AC1 = OLMC 1 and OLMC10 do not have the feedback path ...

Page 5

Input Mode Logic Diagram 1( 120 2(3) 160 280 3(4) 320 440 4(5) 480 600 5(6) 640 760 6(7) 800 920 7(9) 960 1080 8(10) 1120 1240 9(11) 1280 1400 10(12) 1440 1560 11(13) 40-USER ELECTRONIC SIGNATURE ...

Page 6

Feedback Mode OE CLK XOR CLK OE XOR Specifications GAL20XV10 XOR Registered Configuration - SYN = 0. - AC0 = AC1 = 0. - Dedicated CLK input on Pin 1(2 Dedicated OE input on ...

Page 7

Feedback Mode Logic Diagram 1( 120 2(3) 160 280 3(4) 320 440 4(5) 480 600 5(6) 640 760 6(7) 800 920 7(9) 960 1080 8(10) 1120 1240 9(11) 1280 1400 10(12) 1440 1560 11(13) 40-USER ELECTRONIC SIGNATURE ...

Page 8

Absolute Maximum Ratings Supply voltage Vcc ....................................... –0.5 to+7V Input voltage applied .......................... –2.5 to Off-state output voltage applied ......... –2.5 to Storage Temperature ............................... –65 to 150 C Ambient Temperature with Power Applied .......................................... –55 to 125 C 1.Stresses ...

Page 9

AC Switching Characteristics TEST DESCRIPTION PARAMETER 1 COND Input or I/O to Combinatorial Output Clock to Output Delay — Clock to Feedback Delay t su — Setup Time, Input or Feedback ...

Page 10

Switching Waveforms INPUT or VALID INPUT I/O FEEDBACK t pd COMBINATORIAL OUTPUT Combinatorial Output INPUT or I/O FEEDBACK t dis OUTPUT Input or I/O Feedback to Enable/Disable CLK ...

Page 11

Descriptions CLK LOGIC REGISTER ARRAY max with External Feedback 1/( Note: fmax with external feedback is calculated from measured tsu and tco. CLK LOGIC REGISTER ARRAY max with No ...

Page 12

... GAL20XV10 input buffers have active pull-ups within their input structure. This pull-up will cause any un-terminated input or I/O to float to a TTL high (logical 1). Lattice Semiconductor recommends that all unused inputs and tri-stated I/O pins be connected to another active input, Vcc, or GND. Doing this will tend to improve noise immunity and reduce Icc for the device ...

Page 13

Typical AC and DC Characteristic Diagrams Normalized Tpd vs Vcc 1.2 PT H->L 1.1 PT L->H 1 0.9 0.8 4.50 4.75 5.00 5.25 5.50 Supply Voltage (V) Normalized Tpd vs Temp 1.3 PT H->L 1.2 PT L->H 1.1 1 0.9 ...

Page 14

Typical AC and DC Characteristic Diagrams Vol vs Iol 3 2.5 2 1.5 1 0.5 0 0.00 20.00 40.00 60.00 80.00 100.00 Iol (mA) Normalized Icc vs Vcc 1.20 1.10 1.00 0.90 0.80 4.50 4.75 5.00 5.25 5.50 Supply Voltage ...

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