SAB-C165-LM Infineon Technologies, SAB-C165-LM Datasheet - Page 45

• Manufacturer Part Number: SAB-C165-LM
• Description: MCU 16-Bit C166 CISC/RISC ROMLess 5V 100-Pin MQFP
• Manufacturer: Infineon Technologies

Specifications of SAB-C165-LM

• Package: 100MQFP
• Family Name: C166
• Maximum Speed: 20 MHz
• Ram Size: 2 KB
• Operating Supply Voltage: 5 V
• Data Bus Width: 16 Bit
• Program Memory Type: ROMLess
• Number Of Programmable I/os: 77
• Interface Type: ASC/SSC
• Operating Temperature: 0 to 70 °C
• Number Of Timers: 5

Table 9
CLKCFG
(P0H.7-5)
1)
2)
Prescaler Operation
When prescaler operation is configured (CLKCFG = 1XX
from the internal oscillator (input clock signal) by a 2:1 prescaler.
The frequency of
the duration of an individual TCL) is defined by the period of the input clock
The timings listed in the AC Characteristics that refer to TCLs therefore can be
calculated using the period of
Direct Drive
When direct drive is configured (CLKCFG = 0XX
disabled and the CPU clock is directly driven from the internal oscillator with the input
clock signal.
The frequency of
f
f
The timings listed below that refer to TCLs therefore must be calculated using the
minimum TCL that is possible under the respective circumstances. This minimum value
can be calculated via the following formula:
For two consecutive TCLs the deviation caused by the duty cycle of
so the duration of 2TCL is always 1/
be used only once for timings that require an odd number of TCLs (1, 3, …). Timings that
require an even number of TCLs (2, 4, …) may use the formula 2TCL = 1/
Data Sheet
CPU
OSC
0 X X
1 X X
The external clock input range refers to a CPU clock range of 10 … 25 MHz (PLL operation).
The maximum frequency depends on the duty cycle of the external clock signal.
.
TCL
(i.e. the duration of an individual TCL) is defined by the duty cycle of the input clock
min
f
f
= 1/
CPU Frequency
f
OSC
OSC
C165 Clock Generation Modes
CPU
f
f
OSC
f
CPU
/ 2
CPU
=
1
f
OSC
is half the frequency of
directly follows the frequency of
DC
min
F
f
OSC
External Clock
Input Range
1 to 25 MHz
2 to 50 MHz
for any TCL.
(DC = duty cycle)
f
OSC
. The minimum value TCL
41
1)
f
OSC
and the high and low time of
B
) the on-chip phase locked loop is
Notes
Direct drive
CPU clock via prescaler
f
OSC
B
) the CPU clock is derived
so the high and low time of
2)
f
OSC
min
therefore has to
is compensated
f
V2.0, 2000-12
OSC
f
OSC
f
.
CPU
.
C165
(i.e.