AD8151AST Analog Devices Inc, AD8151AST Datasheet - Page 18

• Manufacturer Part Number: AD8151AST
• Description: IC CROSSPOINT SWIT 33X17 184LQFP
• Manufacturer: Analog Devices Inc

Specifications of AD8151AST

• Rohs Status: RoHS non-compliant
• Function: Crosspoint Switch
• Circuit: 1 x 33:17
• Voltage Supply Source: Dual Supply
• Voltage - Supply, Single/dual (±): ±3 V ~ 5.25 V
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 184-LQFP
• Number Of Arrays: 1
• Differential Data Transmission: Yes
• Operating Supply Voltage (typ): Not RequiredV
• Mounting: Surface Mount
• Operating Temperature (max): 85C
• Cascading Capability: No
• Line Code: NRZ
• On-chip Buffers: Yes
• On-chip Mux/demux: No
• Operating Supply Voltage (max): Not RequiredV
• Operating Supply Voltage (min): Not RequiredV
• Lead Free Status / RoHS Status: Not Compliant

AD8151
RE Input
Second Rank Read-Enable. Forcing this pin to logic low enables
the output drivers on the bidirectional D pins [6:0], entering
the readback mode of operation. By selecting an output address
with the A pins [4:0] and forcing RE to logic low, the 7-bit
data stored in the second rank latch for that output address is
written to the D pins [6:0]. Data should not be written to the
D pins [6:0] externally while in readback mode.
The RE and WE pins are not exclusive, and can be used at the
same time, but data should not be written to the D pins [6:0]
from external sources while in readback mode.
CS Input
Chip-Select. This pin must be forced to logic low to program or
receive data from the logic interface, with the exception of the
RESET pin, described in the next section. This pin has no
effect on the signal pairs and does not alter any of the stored
control data.
RESET Input
Global Output Disable Pin. Forcing the RESET pin to logic low
resets the enable bit, D6, in all 17 second rank latches,
regardless of the state of any of the other pins. This has the
effect of immediately disabling the 17 output signal pairs in the
matrix.
Rev. B | Page 18 of 40
It is useful to momentarily hold RESET at a logic low state when
powering up the AD8151 in a system that has multiple output
signal pairs connected together. Failure to do this can result in
several signal outputs contending after power-up. The RESET
pin is not gated by the state of the chip-select pin, CS . It should
be noted that the RESET pin does not program the first rank,
which contains undefined data after power-up.
CONTROL INTERFACE TRANSLATORS
The AD8151 control interface has two supply pins, V
The potential between the positive logic supply, V
negative logic supply, V
5 V. Regardless of supply, the logic threshold is approximately
1.6 V above V
CMOS and TTL logic drivers. The signal matrix supplies, V
and V
with the constraints that (V
allow operation of the control interface on 3 V or 5 V, while the
signal matrix is operated on 3.3 V or 5 V PECL or –3.3 V or
–5 V ECL.
EE
, can be set independently of the voltage on V
SS
, allowing the interface to be used with most
SS
, must be at least 3 V and no more than
DD
− V
EE
) ≤ 10 V. These constraints
DD
, and the
DD
DD
and V
and V
CC
SS
SS
.
,