AD8151AST Analog Devices Inc, AD8151AST Datasheet - Page 19

• Manufacturer Part Number: AD8151AST
• Description: IC CROSSPOINT SWIT 33X17 184LQFP
• Manufacturer: Analog Devices Inc

Specifications of AD8151AST

• Rohs Status: RoHS non-compliant
• Function: Crosspoint Switch
• Circuit: 1 x 33:17
• Voltage Supply Source: Dual Supply
• Voltage - Supply, Single/dual (±): ±3 V ~ 5.25 V
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 184-LQFP
• Number Of Arrays: 1
• Differential Data Transmission: Yes
• Operating Supply Voltage (typ): Not RequiredV
• Mounting: Surface Mount
• Operating Temperature (max): 85C
• Cascading Capability: No
• Line Code: NRZ
• On-chip Buffers: Yes
• On-chip Mux/demux: No
• Operating Supply Voltage (max): Not RequiredV
• Operating Supply Voltage (min): Not RequiredV
• Lead Free Status / RoHS Status: Not Compliant

CIRCUIT DESCRIPTION
The AD8151 is a high speed 33 × 17 differential crosspoint
switch designed for data rates up to 3.2 Gbps per channel. The
AD8151 supports PECL-compatible input and output levels
when operated from a 5 V supply (V
ECL-compatible levels when operated from a –5 V supply
(V
from a +3.3 V supply to interface with low voltage PECL
circuits or a –3.3 V supply to interface with low voltage ECL
circuits. The AD8151 utilizes differential current-mode outputs
with an individual disable control, which facilitates busing the
outputs of multiple AD8151s together to assemble larger switch
arrays. This feature also reduces system crosstalk and can
greatly reduce power dissipation in a large switch array. A single
external resistor programs the current for all enabled output
stages, allowing user control over output levels with different
output termination schemes and transmission line
characteristic impedances.
High Speed Data Inputs (INxxP, INxxN)
The AD8151 has 33 pairs of differential voltage-mode inputs.
The common-mode input range extends from the positive
supply voltage (V
input levels (V
voltage is 200 mV. Unused inputs may be connected directly to
any level within the allowed common-mode input range. A
simplified schematic of the input circuit is shown in Figure 33.
To maintain signal fidelity at the high data rates supported by
the AD8151, the input transmission lines should be terminated
as close to the input pins as possible. The preferred input
termination structure depends primarily on the application and
the output circuit of the data source. Standard ECL components
have open emitter outputs that require pull-down resistors.
Three input termination networks suitable for this type of
source are shown in Figure 34. The characteristic impedance of
the transmission line is shown as Z
in the Thevenin termination are chosen to synthesize a V
source with an output resistance of Z
output voltage equal to V
differential termination scheme are needed to bias the emitter
followers of the ECL source.
CC
= GND, V
INxxP
CC
EE
– 2 V). The minimum differential input
CC
= –5 V). To save power, the AD8151 can run
Figure 33. Simplified Input Circuit
) down to include standard ECL or PECL
CC
– 2 V. The load resistors (RL) in the
V
V
CC
EE
O
. The resistors, R1 and R2,
CC
O
and an open-circuit
= 5 V, V
INxxN
EE
= GND), or
TT
Rev. B | Page 19 of 40
If the AD8151 is driven from a current-mode output stage such
as another AD8151, the input termination should be chosen to
accommodate that type of source, as explained in the following
section.
High speed Data Outputs (OUTyyP, OUTyyN)
The AD8151 has 17 pairs of differential current-mode outputs.
The output circuit, shown in Figure 35, is an open-collector
NPN current switch with resistor-programmable tail current
and output compliance extending from the positive supply
voltage (V
(V
outputs from multiple AD8151s to be connected directly. Since
the output currents of multiple enabled output stages sum when
directly connected, care should be taken to ensure that the
output compliance limit is not exceeded at any time by disabling
the active output driver before enabling an inactive driver.
Figure 34. AD8151 Input Termination from ECL/PECL Sources: (a) Parallel
ECL SOURCE
CC
Termination Using V
− 2 V). The outputs can be disabled individually to permit
V
CC
CC
) down to standard ECL or PECL output levels
ECL SOURCE
Z
Z
O
O
V
V
(a)
Z
TT
CC
O
V
= V
EE
Figure 35. Simplified Output Circuit
V
– 2V
CC
and (c) Differential Termination
CC
TT
– 2V
Supply, (b) Thevenin Equivalent Termination,
Z
R
O
L
INxxN
INxxP
V
EE
DISABLE
R
(c)
OUTyyP
L
ECL SOURCE
Z
Z
O
O
V
V
V
CC
EE
CC
OUTyyN
2Z
I
OUT
O
Z O
Z O
(b)
INxxN
R2
INxxP
R1
V
CC
V
EE
– 2V
AD8151
R2
R1
INxxN
INxxP