MT45W8MW16BGX-701 ITTR Micron Technology Inc, MT45W8MW16BGX-701 ITTR Datasheet - Page 17

• Manufacturer Part Number: MT45W8MW16BGX-701 ITTR
• Manufacturer: Micron Technology Inc

Specifications of MT45W8MW16BGX-701 ITTR

• Lead Free Status / Rohs Status: Compliant

Low-Power Operation
Standby Mode
Temperature-Compensated Refresh (TCR)
Partial-Array Refresh (PAR)
Deep Power-Down Mode (DPD)
Registers
PDF: 09005aef80ec6f79/Source: 09005aef80ec6f65
128mb_burst_cr1_5_p26z__2.fm - Rev. H 9/07 EN
During standby, the device current consumption is reduced to the level necessary to
perform the DRAM refresh operation. Standby operation occurs when CE# is HIGH.
The device will enter a reduced power state upon completion of a READ or WRITE oper-
ation, or when the address and control inputs remain static for an extended period of
time. This mode will continue until a change occurs to the address or control inputs.
TCR allows for adequate refresh at different temperatures. This CellularRAM device
includes an on-chip temperature sensor that automatically adjusts the refresh rate
according to the operating temperature. The device continually adjusts the refresh rate
to match that temperature.
PAR restricts refresh operation to a portion of the total memory array. This feature
enables the device to reduce standby current by refreshing only that part of the memory
array required by the host system. The refresh options are full array, one-half array, one-
quarter array, one-eighth array, or none of the array. The mapping of these partitions can
start at either the beginning or the end of the address map. (See Table 7 on page 32.)
READ and WRITE operations to address ranges receiving refresh will not be affected.
Data stored in addresses not receiving refresh will become corrupted. When re-enabling
additional portions of the array, the new portions are available immediately upon
writing to the RCR.
DPD mode disables all refresh-related activity. This mode is used if the system does not
require the storage provided by the CellularRAM device. Any stored data will become
corrupted when DPD is enabled. When refresh activity has been re-enabled, the Cellu-
larRAM device will require 150µs to perform an initialization procedure before normal
operations can resume. During this 150µs period, the current consumption will be
higher than the specified standby levels, but considerably lower than the active current
specification.
DPD can be enabled by writing to the RCR using CRE or the software access sequence;
DPD starts when CE# goes HIGH. DPD is disabled the next time CE# goes LOW and stays
LOW for at least 10µs.
Two user-accessible configuration registers define the device operation. The BCR defines
how the CellularRAM interacts with the system memory bus and is nearly identical to its
counterpart on burst mode Flash devices. The RCR is used to control how refresh is
performed on the DRAM array. These registers are automatically loaded with default
settings during power-up, and can be updated any time the devices are operating in a
standby state.
A DIDR provides information on the device manufacturer, CellularRAM generation, and
the specific device configuration. The DIDR is read-only.
128Mb: 8 Meg x 16 Async/Page/Burst CellularRAM 1.5 Async/
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Micron Technology, Inc., reserves the right to change products or specifications without notice.
Page/Burst CellularRAM 1.5 Memory
©2004 Micron Technology, Inc. All rights reserved.