MT45W8MW16BGX-701 ITTR Micron Technology Inc, MT45W8MW16BGX-701 ITTR Datasheet - Page 65

• Manufacturer Part Number: MT45W8MW16BGX-701 ITTR
• Manufacturer: Micron Technology Inc

Specifications of MT45W8MW16BGX-701 ITTR

• Lead Free Status / Rohs Status: Compliant

Figure 53:
PDF: 09005aef80ec6f79/Source: 09005aef80ec6f65
128mb_burst_cr1_5_p26z__2.fm - Rev. H 9/07 EN
DQ[15:0]
LB#/UB#
A[22:0]
ADV#
WAIT
WE#
OE#
CLK
CE#
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
IL
IL
IH
IL
IH
IL
IH
IL
IH
IL
IH
OL
IH
IH
IL
OH
OL
OH
Burst READ Followed by Asynchronous WRITE Using ADV#
Notes:
READ Burst Identified
Valid Address
t SP
t CSP
(WE# = HIGH)
t SP
t SP
t SP
t CEW
1. Non-default BCR settings for burst READ followed by asynchronous WRITE using ADV#:
2. When transitioning between asynchronous and variable-latency burst operations, CE# must
t HD
t HD
t HD
Fixed or variable latency; latency code two (three clocks); WAIT active LOW; WAIT asserted
during delay.
go HIGH. CE# can stay LOW when transitioning from fixed-latency burst READs; asynchro-
nous operation begins at the falling edge of ADV#. A refresh opportunity must be provided
every
clocked CE# HIGH, or b) CE# HIGH for longer than 15ns.
High-Z
t
CEM. A refresh opportunity is satisfied by either of the following two conditions: a)
128Mb: 8 Meg x 16 Async/Page/Burst CellularRAM 1.5 Async/
t OLZ
t BOE
t ACLK
t KHTL
t CLK
Valid Output
65
t HD
t KOH
t HD
t OHZ
t HZ
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t CBPH
Note 2
Page/Burst CellularRAM 1.5 Memory
High-Z
t CEW
t AS
V
V
IL
IH
Valid Address
t VP
t AVS
t AS
t AVH
t CW
t BW
t AW
©2004 Micron Technology, Inc. All rights reserved.
t WP
Don’t Care
t VS
Valid Input
t DW
t HZ
Undefined
t WPH
t DH