KMPC8548EVTAUJC Freescale Semiconductor, KMPC8548EVTAUJC Datasheet

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... For specific PVR and SVR numbers, refer to the MPC8548E PowerQUICC III Integrated Processor Family Reference Manual. © 2010 Freescale Semiconductor, Inc. All rights reserved. Document Number: MPC8548EEC Rev. 7, 09/2010 Contents 1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2. Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . 10 3 ...

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... PCI Bus Interface Figure 1. MPC8548E Block Diagram e500 Core 32-Kbyte L1 32-Kbyte Instruction L1 Data Cache Cache Serial RapidIO or 4x RapidIO PCI Express x8 PCI Express PCI 32-bit 66 MHz (If 64-bit not used) 32-bit PCI/ PCI/PCI-X 64-bit PCI/PCI-X 133 MHz Bus Interface 4-Channel DMA Controller Freescale Semiconductor ...

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... Four banks of memory supported, each Gbytes maximum of 16 Gbytes — DRAM chip configurations from 64 Mbits to 4 Gbits with ×8/×16 data ports — Full ECC support — Page mode support – simultaneous open pages for DDR MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7 Freescale Semiconductor Overview 3 ...

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... DEU—Data Encryption Standard execution unit – DES, 3DES – Two key (K1, K2) or three key (K1, K2, K3) – ECB and CBC modes for both DES and 3DES MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev and F(p) modes and programmable field size Freescale Semiconductor ...

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... The 32-, 16-, and 8-bit port sizes are controlled by an on-chip memory controller. — Three protocol engines available on a per chip select basis: – General-purpose chip select machine (GPCM) – Three user programmable machines (UPMs) MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7 Freescale Semiconductor 2 C addressing mode Overview 2 ...

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... CRC generation and verification of inbound/outbound frames — Programmable Ethernet preamble insertion and extraction bytes — MAC address recognition: – Exact match on primary and virtual 48-bit unicast addresses MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev Section 8.1, “Enhanced for Freescale Semiconductor ...

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... One 32-bit PCI port with support for speeds from MHz (available when the other port is in 32-bit mode) — Host and agent mode support — 64-bit dual address cycle (DAC) support — PCI-X supports multiple split transactions — Supports PCI-to-memory and memory-to-PCI streaming MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7 Freescale Semiconductor Overview 7 ...

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... Capable of receiving three letters at any mailbox — Two outbound data message structures within the outbox — Capable of sending three letters simultaneously — Single segment multicast devIDs — Chaining and direct modes in the outbox MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev Freescale Semiconductor ...

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... Supports large block (4-Kbyte) uploads and downloads — Supports continuous bit streaming of entire block for fast upload and download • JTAG boundary scan, designed to comply with IEEE Std. 1149.1™ MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7 Freescale Semiconductor Overview 9 ...

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... V — –0.3 to 1.98 –0.3 to 3.63 V –0.3 to 2.75 –0.3 to 3.63 –0.3 to 2.75 –0.3 to 3.63 V — –0.3 to 3.63 V — –0.3 to 2.75 –0.3 to ( –0 — ( 0.3) DD –0.3 to ( –0.3 to (TV + 0.3) DD –0.3 to (BV + 0.3) — — DD –0.3 to ( –0.3 to ( Freescale Semiconductor ...

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... DDR and DDR2 DRAM reference Three-speed Ethernet signals Local bus signals PCI, DUART, SYSCLK, system control and power 2 management Ethernet MII management, and JTAG signals MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7 Freescale Semiconductor 1 (continued) Symbol Max Value T –55 to 150 STG Table 2 ...

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... Not to Exceed 10 references SYSCLK. CLOCK references MCLK. references EC_GTX_CLK125. CLOCK references LCLK. references PCIn_CLK or SYSCLK. references SD_REF_CLK. CLOCK Recommended Symbol Unit Value ° 105 and not necessarily the voltage 1 CLOCK /OV /LV /BV / Table and LV DD Freescale Semiconductor Notes — 2. The based DD REF ...

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... In order to guarantee MCKE low during power-up, the above sequencing for GV is required. If there is no concern about any of the DDR signals being indeterminate state during power-up, then the sequencing for GV not required. MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7 Freescale Semiconductor Table 3. Output Drive Capability Programmable Output Impedance (Ω ...

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... Table 5. SYSCLK AC Timing Specifications Table 2) with OV = 3.3 V ± 165 mV DD Symbol Min f 16 SYSCLK t 7.5 SYSCLK 0 KHK SYSCLK Typical-105 Maximum 7.5 8.1 7.9 8.5 8.3 8.9 16.5 18.6 10.8 12.8 . Typ Max Unit — 133 MHz — 1.0 1.2 ns — Freescale Semiconductor Unit Notes ...

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... The minimum pulse width of the RTC signal should be greater than 2x the period of the CCB clock. That is, minimum clock high time is 2 × minimum RTC frequency; RTC may be grounded if not needed. MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7 Freescale Semiconductor Table 2) with OV = 3.3 V ± 165 mV ...

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... MHz 8 — ns — ns 0.75 1.0 — 2.5 V, and from 0.6 and 2.7 V for DD for duty cycle for 10Base-T and Table 7 provides the . Typ Max Unit — 133 MHz — 1.0 2.1 ns — Freescale Semiconductor Notes — Notes — — ...

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... Section 17.4, “1x/4x LP-Serial Signal Descriptions,” for serial RapidIO interface width and frequency details. 4.7 Other Input Clocks For information on the input clocks of other functional blocks of the platform see the specific section of this document. MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7 Freescale Semiconductor 527 MHz × (PCI-Express link width Input Clocks 17 ...

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... Section 21.2, “PLL Power Supply Filtering,” Min Max Unit Notes μs 100 — — 3 — SYSCLKs μs 100 — — 4 — SYSCLKs 2 — SYSCLKs — 5 SYSCLKs Min Max Unit μs — 100 μs — 50 μs — 50 Max Unit Notes 3500 V/s 1 4000 V the Freescale Semiconductor ...

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... DDR2 I/O capacitance when GV Table 12. DDR2 SDRAM Capacitance for GV Parameter/Condition Input/output capacitance: DQ, DQS, DQS Delta input/output capacitance: DQ, DQS, DQS Note: 1. This parameter is sampled MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7 Freescale Semiconductor . Symbol Min GV 1.71 DD 0.49 × REF ...

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... Max Unit 2.625 V 0.51 × 0.04 V REF – 0.15 V REF μA 50 — mA — (typ Min Max Unit — 0 /2, V (peak-to-peak) = 0.2 V. OUT DD OUT REF Min Max Unit μA — 500 Freescale Semiconductor Notes — — 4 — — Notes 1 1 Notes 1 ...

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... MDQS[n]. This should be subtracted from the total timing budget. 2. The amount of skew that can be tolerated from MDQS to a corresponding MDQ signal is called t determined by the following equation: t absolute value CISKEW MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7 Freescale Semiconductor Symbol Symbol ...

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... MHz 538 400 MHz 700 333 MHz 900 –0.5 × DDKHMP MCK Max Unit — — — ns — — — ns — — — ns — — — 0 — — — ps — — — –0.5 × t – 0.6 + 0.6 ns MCK Freescale Semiconductor Notes ...

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... Figure 3 shows the DDR SDRAM output timing for the MCK to MDQS skew measurement (t MCK[n] MCK[n] MDQS MDQS MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7 Freescale Semiconductor 1 Symbol Min t –0.6 DDKHME (first two letters of functional block)(signal)(state)(reference)(state) for outputs ...

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... Figure 4. DDR SDRAM Output Timing Diagram Figure 5 provides the AC test load for the DDR bus. Output MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev MCK DDKHAS DDKHCS DDKHAX DDKHCX NOOP t DDKHMP t DDKHMH t DDKHDS t DDKLDS DDKHDX = 50 Ω Ω Figure 5. DDR AC Test Load t DDKHME t DDKLDX Freescale Semiconductor ...

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... Notes: 1. Guaranteed by design refers to the internal platform clock. CCB 3. Actual attainable baud rate is limited by the latency of interrupt processing. 4. The middle of a start bit is detected as the 8 th sampled each 16 sample. MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7 Freescale Semiconductor Symbol –2 mA ...

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... The RGMII and RTBI signals are based on a 2.5-V CMOS Symbol Min LV 3. –4.0 mA 4.0 mA) V GND 2 –0 — –600 IL and TV symbols referenced Section 9, “Ethernet Section 9, “Ethernet Max Unit Notes 3. /TV + 0.3 V — 0.50 V — LV /TV + 0.3 V — 0.90 V — μ μA — — Table 1 and Table 2. Freescale Semiconductor ...

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... Note that there is relationship between the maximum FIFO speed and the platform speed. For more information see Section 4.5, “Platform to FIFO Restrictions.” MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7 Freescale Semiconductor Symbol Min LV /TV 2 ...

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... Min Typ Max 5.3 8.0 100 FIR / FIR — — 250 — — 0.75 — — 0.75 1.5 — — 0.5 — — Section 4.5, “Platform to FIFO Restrictions.” t FITR Freescale Semiconductor Unit Unit ...

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... For example, the subscript of t GTX used with the appropriate letter: R (rise (fall). 2. Guaranteed by design. MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7 Freescale Semiconductor t FIR Valid Data t t ...

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... GMII (G) receive (RX) clock. For rise and fall times, the latter convention = 50 Ω Figure 9. eTSEC AC Test Load t GTXR 1 Min Typ Max — 8.0 — 35 — 75 2.0 — — 0 — — — — 1.0 — — 1.0 symbolizes GMII receive GRDVKH clock reference ( Ω Freescale Semiconductor Unit for ...

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... For example, the subscript of t MTX used with the appropriate letter: R (rise (fall). 2. Guaranteed by design. MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7 Freescale Semiconductor t GRX t t GRXF ...

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... Note that, in general, MRX = 50 Ω Figure 12. eTSEC AC Test Load t MTXR Min Typ Max — 400 — — 40 — 35 — 65 10.0 — — 10.0 — — 1.0 — 4.0 1.0 — 4.0 symbolizes MII receive MRDVKH clock reference (K) MRX Ω Freescale Semiconductor Unit for ...

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... For example, the subscript of t represents the TBI (T) transmit (TX) clock. For rise and fall times, the latter convention is used with the appropriate TTX letter: R (rise (fall). 2. Guaranteed by design. MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7 Freescale Semiconductor t MRX t t MRXH MRXF ...

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... Note that, in general, the clock TRX t TTXR t TTXR t TTKHDX Min Typ Max — 16.0 — 7.5 — 8.5 40 — 60 2.5 — — 1.5 — — 0.7 — 2.4 0.7 — 2.4 symbolizes TBI receive TRDVKH clock reference (K) TRX Freescale Semiconductor Unit for ...

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... RX_CLK duty cycle RX_CLK peak-to-peak jitter Rise time RX_CLK (20%–80%) Fall time RX_CLK (80%–20%) RCG[9:0] setup time to RX_CLK rising edge RCG[9:0] hold time to RX_CLK rising edge MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7 Freescale Semiconductor t TRX t t TRXH TRXF Valid Data ...

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... TBI (T) receive (RX) clock. Note also that the notation for rise RGT is -650 ps (min) and 650 ps (max). Refer to “eTSEC 10” in the device errata document. t TRRR t TRRF Min Typ Max 6 6 –500 0 500 1.0 — 2.8 7.2 8.0 8 — — 0.75 — — 0.75 of the lowest speed transitioned RGT Freescale Semiconductor Unit ...

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... The RMII transmit AC timing specifications are in Table 34. RMII Transmit AC Timing Specifications Parameter/Condition TSECn_TX_CLK clock period TSECn_TX_CLK duty cycle TSECn_TX_CLK peak-to-peak jitter Rise time TSECn_TX_CLK (20%–80%) Fall time TSECn_TX_CLK (80%–20%) MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7 Freescale Semiconductor t RGTH t SKRGT TXD[8:5] TXD[3:0] TXD[7:4] TXD[9] ...

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... MII transmit MTKHDX t RMTR 1 Min Typ Max 15.0 20.0 25 — — 250 1.0 — 2.0 1.0 — 2.0 4.0 — — 2.0 — — symbolizes MII receive MRDVKH clock reference (K) MRX Freescale Semiconductor Unit ns for Unit for ...

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... Supply voltage (3.3 V) Output high voltage (OV = Min Output low voltage (OV = Min Input high voltage Input low voltage MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7 Freescale Semiconductor Ethernet Management Interface Electrical Characteristics = 50 Ω Figure 19. eTSEC AC Test Load t RMR t t RMRF RMRH ...

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... MDKHDX CCB = 533) ÷ (2 × 4 × 533) ÷ MDC ), the ECn_MDC output clock frequency can be CCB ÷ 448. Refer to MPC8572E reference manual’s CCB Freescale Semiconductor Unit μA μA Notes — — — — for ). The actual ...

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... Low-level input voltage 1 Input current ( High-level output voltage (BV = min Low-level output voltage (BV = min Note: 1. Note that the symbol this case, represents the BV IN MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7 Freescale Semiconductor t MDC t t MDCH MDCF t MDDVKH t MDDXKH t MDKHDX Symbol ...

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... LBIVKH2 t 1.0 — LBIXKH1 t 1.0 — LBIXKH2 t 1.5 — LBOTOT t — 2.0 LBKHOV1 t — 2.2 LBKHOV2 t — 2.3 LBKHOV3 t — 2.3 LBKHOV4 t 0.7 — LBKHOX1 t 0.7 — LBKHOX2 t — 2.5 LBKHOZ1 Freescale Semiconductor Unit V V μ Notes — — ...

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... Local bus clock to address valid for LAD Local bus clock to LALE assertion Output hold from local bus clock (except LAD/LDP and LALE) Output hold from local bus clock for LAD/LDP MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7 Freescale Semiconductor = 3.3 V)—PLL Enabled (continued) DD Symbol t ...

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... LSYNC_IN for PLL enabled or internal local bus clock for PLL = 50 Ω Figure 22. Local Bus AC Test Load NOTE 1 Min Max Unit — 2.6 ns — 2.6 ns symbolizes local bus LBIXKH1 clock reference (K) goes high (H), in this case for LBOTOT Ω L Freescale Semiconductor Notes 5 5 for is ...

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... LGTA/LUPWAIT input hold from local bus clock LALE output transition to LAD/LDP output transition (LATCH hold time) Local bus clock to output valid (except LAD/LDP and LALE) Local bus clock to data valid for LAD/LDP MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7 Freescale Semiconductor t LBIVKH1 t LBIVKH2 ...

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... PLL bypass mode to 0.4 × Min Max Unit — — –3.7 — ns –3.7 — ns — 0.2 ns — 0.2 ns symbolizes local bus LBIXKH1 clock reference (K) goes high (H), in this case for of the signal DD Freescale Semiconductor Notes for ...

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... In PLL bypass mode, LCLK[n] is the inverted version of the internal clock with the delay of of the internal clock and are captured at falling edge of the internal clock with the exception of LGTA/LUPWAIT (which is captured on the rising edge of the internal clock). MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7 Freescale Semiconductor t LBKHKT t LBKLOV1 t ...

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... LUPWAIT Input Signals: LAD[0:31]/LDP[0:3] UPM Mode Output Signals: LCS[0:7]/LBS[0:3]/LGPL[0:5] Figure 25. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV (PLL Enabled) MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev LBKHOV1 LBKHOZ1 t LBIVKH2 t LBIVKH1 t t LBKHOV1 LBKHOZ1 t LBIXKH2 t LBIXKH1 Freescale Semiconductor ...

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... UPM Mode Input Signal: LUPWAIT Input Signals: LAD[0:31]/LDP[0:3] UPM Mode Output Signals: LCS[0:7]/LBS[0:3]/LGPL[0:5] Figure 26. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV (PLL Bypass Mode) MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7 Freescale Semiconductor t t LBKLOX1 LBKLOV1 t LBIVKH1 Local Bus ...

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... LUPWAIT Input Signals: LAD[0:31]/LDP[0:3] UPM Mode Output Signals: LCS[0:7]/LBS[0:3]/LGPL[0:5] Figure 27. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV (PLL Enabled) MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev LBKHOV1 LBKHOZ1 t LBIVKH2 t LBIVKH1 t t LBKHOV1 LBKHOZ1 t LBIXKH2 t LBIXKH1 Freescale Semiconductor ...

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... In IRQ edge trigger mode, when an external interrupt signal is asserted (according to the programmed polarity), it must remain the assertion for at least 3 system clocks (SYSCLK periods). 12 JTAG This section describes the DC and AC electrical specifications for the IEEE 1149.1 (JTAG) interface of the MPC8548E. MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7 Freescale Semiconductor t t LBKLOX1 LBKLOV1 t ...

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... JTKLDX TDO t JTKLOX Min Max 0.3 DD –0.3 0.8 — ±5 2.4 — — 0.4 Figure 30 through Figure 32. 1 Min Max Unit Notes 0 33.3 MHz 30 — — — — 0 — — 25 — — 30 — Freescale Semiconductor Unit V V μ — — — ...

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... Figure 30 provides the JTAG clock input timing diagram. JTAG External Clock Figure 30. JTAG Clock Input Timing Diagram Figure 31 provides the TRST timing diagram. TRST MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7 Freescale Semiconductor 2 Symbol Boundary-scan data t JTKLDZ TDO t JTKLOZ (first two letters of functional block)(signal)(state)(reference)(state) for outputs ...

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... Figure 32. Boundary-Scan Timing Diagram 2 C interfaces. 2 Table 45 Electrical Characteristics Symbol 0.7 × I2KHKL switched off JTDXKH Input Data Valid Output Data Valid 2 C interfaces of the MPC8548E. Min Max Unit 0.3 × OV –0 0.2 × μA –10 10 — Freescale Semiconductor Notes — — — ...

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... C frequency calculation, refer to Freescale Application Note AN2919, Determining the I Divider Ratio for SCL. Note that the I 3. The maximum t has only to be met if the device does not stretch the LOW period (t I2DXKL 4. Guaranteed by design. MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7 Freescale Semiconductor 2 C interfaces. 2 Table 46 Electrical Specifications 1 ...

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... I2DXKL, I2OVKL Sr 2 Figure 34 Bus AC Timing Diagram Symbol – symbol referenced Ω I2KHKL I2CF t I2CR t I2PVKH P 1 Min Max Unit 0 –0.3 0.8 V μA — ±5 2.4 — V — 0.4 V Table 1 and Table 2. Freescale Semiconductor S Notes — — 2 — — ...

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... PCI 2.2 Local Bus PCRHFV Specifications. 9. The reset assertion timing requirement for HRESET is 100 μs. 10.Guaranteed by characterization. 11.Guaranteed by design. Figure 35 provides the AC test load for PCI and PCI-X. Output MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7 Freescale Semiconductor 1 Symbol t PCKHOV t PCKHOX t PCKHOZ t ...

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... MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev PCIVKH CLK t PCKHOV t PCKHOZ Output Symbol t PCKHOV t PCKHOX t PCKHOZ t PCIVKH t PCIXKH t PCRVRH t PCRHRX t PCRHFV t PCIVRH t PCIXKH Min Max Unit Notes — 3 0.7 — — 1.7 — 0.5 — — clocks — clocks — clocks 11 Freescale Semiconductor ...

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... Input setup time to SYSCLK Input hold time from SYSCLK REQ64 to HRESET setup time HRESET to REQ64 hold time HRESET high to first FRAME assertion PCI-X initialization pattern to HRESET setup time MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7 Freescale Semiconductor Symbol Min Max ...

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... The figure shows a waveform for either a transmitter output (SD_TX and SD_TX receiver input (SD_RX and SD_RX). Each signal swings between A volts and B volts where A > B. MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev Symbol Min Max PCRHIX and t only in PCI-X mode. In conventional PCKHOV CYC Freescale Semiconductor Unit Notes PCRHFV ...

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... Sometimes, it may be even different between the receiver input and driver output circuits within the same component also referred to as the DC offset. MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7 Freescale Semiconductor (or differential output swing): OD – ...

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... MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev Differential Swing Differential Peak Voltage, V Differential Peak-Peak Voltage, V DIFFpp is 500 mV in one phase and –500 mV in the other phase. The peak OD are specified in DD_SRDS2 B)/ – – B| DIFFp = 2*V (not shown) DIFFp ) is 1000 mVp-p. DIFFp-p Table 1 and Table 2. Freescale Semiconductor ) OD ...

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... This requirement is the same for both external DC- or AC-coupled connection. — For external DC-coupled connection, as described in Receiver Characteristics,” MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7 Freescale Semiconductor 50 Ω Input Amp 50 Ω ...

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... MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev Figure 40 Figure 41 shows the SerDes reference clock min Figure 42 V max 100 mV < < V max cm V > V min cm Freescale Semiconductor shows the with max shows < 800 mV < 400 mV V > min + 400 – 400 mV ...

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... They might also vary from one vendor to the other. Therefore, Freescale Semiconductor can neither provide the optimal clock driver reference circuits, nor guarantee the correctness of the following clock driver connection reference circuits. The system designer is recommended ...

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... MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev SD_REF_CLK 100 Ω Differential PWB Trace SD_REF_CLK Clock driver vendor dependent source termination resistor SD_REF_CLK 100 Ω Differential PWB Trace SD_REF_CLK MPC8548E 50 Ω SerDes Refer. CLK Receiver 50 Ω MPC8548E 50 Ω SerDes Refer. CLK Receiver 50 Ω Figure 45 Freescale Semiconductor ...

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... It assumes the DC levels of the clock driver are compatible with the MPC8548E SerDes reference clock input’s DC requirement. Single-Ended CLK Driver Chip 33 Ω Clock Driver CLK_Out Figure 46. Single-Ended Connection (Reference Only) MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7 Freescale Semiconductor SD_REF_CLK 100 Ω Differential PWB Trace SD_REF_CLK Total 50 Ω ...

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... PCI Express This section describes the DC and AC electrical specifications for the PCI Express bus of the MPC8548E. MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev SD_TXn SD_RXn SD_TXn SD_RXn 50 Ω Receiver 50 Ω Freescale Semiconductor ...

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... Symbol Parameter UI Unit interval V Differential TX-DIFFp-p peak-to-peak output voltage MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7 Freescale Semiconductor Min Nom Max Unit 399.88 400 400.12 ps Each UI is 400 ps ± 300 ppm. UI does not account for spread spectrum clock dictated variations. ...

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... T = 0.3 UI. TX-EYE = relation TX-DIFFp-p = RMS(| |/2 – TXD+ TXD– |/2. (avg) TX-D+ TX-D– TX-CM-Idle-DC (during | ≤ 100 |/2 [L0] (avg) TX-D+ TX-D– |/2 (avg) TX-D+ TX-D– | ≤ – V TX-CM-DC-D– (avg) TX- (avg) TX-D– – TX-IDLE-D+ TX-IDLE-D– Freescale Semiconductor ...

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... L Lane-to-lane TX-SKEW output skew C AC coupling TX capacitor MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7 Freescale Semiconductor Min Nom Max Unit 50 — UI Minimum time a transmitter must be in electrical idle utilized by the receiver to start looking for an electrical idle exit after successfully receiving an electrical idle ordered set — ...

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... TX-EYE-MEDIAN-to-MAX-JITTER is specified using the passive compliance/test measurement load (see NOTE Comments Figure 50 and measured over Figure 48.) = 0.30 UI for the TX-JITTER-MAX median is less than half of the total Figure 50). Note that the series capacitors Figure 50 for both V and V TX-D+ TX-D– Freescale Semiconductor . ...

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... T Maximum time RX-EYE-MEDIAN-to- between the MAX-JITTER jitter median and maximum deviation from the median MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7 Freescale Semiconductor [Transition Bit 800 mV TX-DIFFp-p-MIN [De-Emphasized Bit] 566 mV (3 dB) >= V >= 505 mV (4 dB) TX-DIFFp-p-MIN 0. – 0 TX-TOTAL-MAX [Transition Bit] ...

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... Measured at the package pins of the receiver — — unexpected electrical idle (V V RX-IDLE-DET-DIFFp-p longer than T an unexpected idle condition. Comments = |V – RXD+ RXD- RX-CM-DC | ÷ (avg) RX-D+ RX-D– × |V –V |. RX-D+ RX-D– < RX-DIFFp-p ) must be recognized no to signal RX-IDLE-DET-DIFF-ENTERING Freescale Semiconductor ...

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... RX package and silicon. The RX eye diagram must be aligned in time using the jitter median to locate the center of the eye diagram. MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7 Freescale Semiconductor Min Nom Max Unit — ...

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... Figure 50. Compliance Test/Measurement Load MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev NOTE Figure 50). Note that the series capacitors, CTX, are V > 175 mV RX-DIFFp-p-MIN 0 RX-EYE-MIN NOTE Pin Pin Silicon + Package Ω Pin RX-DIFF (D+ D– Crossing Point) Figure 50 Ω Freescale Semiconductor ...

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... REFCLK cycle-to-cycle jitter. Difference in the REFCJ period of any two adjacent REFCLK cycles. t Phase jitter. Deviation in edge location with REFPJ respect to mean edge location. MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7 Freescale Semiconductor Min Typ Max Unit — 10(8) — applies only to serial ...

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... The use of active circuits in the receiver. This is often referred to as adaptive equalization. MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev Figure 51 shows how the signals are defined. The figures show , is defined defined Differential Peak-to-Peak = 2 × (A – B) – – Freescale Semiconductor ...

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... DIFFPP Deterministic jitter J D Total jitter J T Multiple output skew S MO Unit Interval UI MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7 Freescale Semiconductor Range Unit Min Max –0.40 2.30 V Voltage relative to COMMON of either signal comprising a differential pair 500 1000 mV p-p — ...

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... UI p-p — 0.35 UI p-p — 1000 ps Skew at the transmitter output between lanes of a multilane link 800 800 ps ±100 ppm Notes — — — Notes — — — Notes — — — Freescale Semiconductor ...

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... Figure 52 with the parameters specified in the device is driving a 100-Ω ± 5% differential resistive load. The output eye pattern of an LP-serial MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7 Freescale Semiconductor Range Unit Min Max –0.40 2 ...

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... MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev Time min (mV) V max (mV) DIFF DIFF 250 500 400 800 250 500 400 800 250 500 400 800 1-B 1-A A (UI) B (UI) 0.175 0.39 0.175 0.39 0.175 0.39 0.175 0.39 0.175 0.39 0.175 0.39 Freescale Semiconductor 1 ...

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... Total jitter is composed of three components, deterministic jitter, random jitter, and single frequency sinusoidal jitter. The sinusoidal jitter may have any amplitude and frequency in the unshaded region of is included to ensure margin for low frequency jitter, wander, noise, crosstalk, and other variable system effects. MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7 Freescale Semiconductor Range Symbol Unit ...

Page 84

... DR J 0.65 — — -12 BER — 320 320 ps Frequency Notes Measured at receiver Measured at receiver Measured at receiver Measured at receiver Skew at the receiver input between lanes of a multilane link — ±100 ppm Figure 53. The sinusoidal jitter component 1.875 MHz 20 MHz Freescale Semiconductor ...

Page 85

... Since the LP-serial electrical specification are guided by the XAUI electrical interface specified in Clause 47 of IEEE Std. 802.3ae-2002, the measurement and test requirements defined here are similarly guided by Clause 47. In addition, the CJPAT test pattern defined in Annex 48A of IEEE Std. 802.3ae-2002 MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7 Freescale Semiconductor (Table 62, Table ...

Page 86

... MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev Figure 54 and Table 65. Note that for this to occur, the test signal must Section 17.7, “Receiver Specifications,” Continuous Jit Section 17.7, “Receiver Specifications,” Freescale Semiconductor –12 . ter test is ...

Page 87

... Full Lid Figure 55 shows the mechanical dimensions and bottom surface nomenclature for both the MPC8548E HiCTE FC-CBGA and FC-PBGA package with full lid. MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7 Freescale Semiconductor Table 66. Package Parameters 1 CBGA 29 mm × 783 ...

Page 88

... MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev 28.7 MAX 29 LID ZONE 27X 1 27X 1 0.5 0 783X 0 0 0.15 A FC-CBGA and FC-PBGA with Full Lid 0.2 A 783X 0.25 A SEATING 0. 1.63 1.37 3 3.38 MAX SIDE VIEW Freescale Semiconductor A PLANE 4 0.6 0.35 1.32 1.08 ...

Page 89

... PCI1_PAR PCI1_PERR PCI1_SERR PCI1_STOP PCI1_TRDY MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7 Freescale Semiconductor NOTE Table 67. MPC8548E Pinout Listing Package Pin Number PCI1 and PCI2 (One 64-Bit or Two 32-Bit) AB14, AC15, AA15, Y16, W16, AB16, AC16, AA16, AE17, AA18, W18, AC17, AD16, AE16, ...

Page 90

... B8, E10, B10, G6, A10, L11 F7, J7, M11 Power Pin Type Notes Supply I OV — DD — — — — I/O OV — I I — I/O OV — — DD I/O OV — DD I/O GV — DD I/O GV — — DD I/O GV — DD I/O GV — — — DD Freescale Semiconductor ...

Page 91

... LALE LBCTL LGPL0/LSDA10 LGPL1/LSDWE LGPL2/LOE/LSDRAS LGPL3/LSDCAS LGPL4/LGTA/LUPWAIT/LPBSE LGPL5 LCKE LCLK[0:2] MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7 Freescale Semiconductor Package Pin Number F10, C10, J11, H11 K8, J8, G8, F8 H9, B15, G2, M9, A14, F1 J9, A15, G1, L9, B14, F2 E6, K6, L7, M7 A19, B19 Local Bus Controller Interface ...

Page 92

... Gigabit Reference Clock V11 R5, U1, R3, U2, V3, V1, T3, T2 T10, V7, U10, U5, U4, V6, T5 Power Pin Type Notes Supply I BV — — 102 I OV — — — — — — I I I/O OV — — — — — — — — — — DD Freescale Semiconductor ...

Page 93

... TSEC3_TX_EN Three-Speed Ethernet Controller (Gigabit Ethernet 4) TSEC4_TXD[3:0]/TSEC3_TXD[7:4] TSEC4_RXD[3:0]/TSEC3_RXD[7:4] TSEC4_GTX_CLK TSEC4_RX_CLK/TSEC3_COL TSEC4_RX_DV/TSEC3_CRS TSEC4_TX_EN/TSEC3_TX_ER UART_CTS[0:1] UART_RTS[0:1] UART_SIN[0:1] UART_SOUT[0:1] MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7 Freescale Semiconductor Package Pin Number P2, R2, N1, N2, P3, M2, M1, N3 N9, N10, P8, N7, R9, N5, R8 P10 P7 R10 V8, W10, Y10, W7 ...

Page 94

... AG16 AG20 AA9 AA8 Debug AB2 AB1 AE4, AG2 AF3, AF1, AF2 AE5 AE21 Power Pin Type Notes Supply — — — — — — 2 — — 32 — — 34 — — — — — — — 19 19 Freescale Semiconductor ...

Page 95

... TCK TDI TDO TMS TRST L1_TSTCLK L2_TSTCLK LSSD_MODE TEST_SEL THERM0 THERM1 ASLEEP GND OV DD MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7 Freescale Semiconductor Package Pin Number Clock AF16 AH17 JTAG AG28 AH28 AF28 AH27 AH23 DFT AC25 AE22 AH20 AH14 ...

Page 96

... V) Power for local — 26 bus PLL (1.1 V) Power for PCI1 — 26 PLL (1.1 V) Power for PCI2 — 26 PLL (1.1 V) Power for e500 — 26 PLL (1.1 V) Power for CCB — 26 PLL (1.1 V) Power for — 26 SRDSPLL (1 — — 13 Freescale Semiconductor ...

Page 97

... FIFO mode when used as Rx flow control. 24.Do not connect. MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7 Freescale Semiconductor Package Pin Number Analog Signals A18 L28 ...

Page 98

... MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev Package Pin Number . through 2–10 kΩ resistors if they are not used. DD through 2–10 kΩ resistors. DD through 2–10 kΩ resistors. DD Power Pin Type Notes Supply for normal machine operation through an 18.2-Ω precision DD ) through DD ) through DD Freescale Semiconductor ...

Page 99

... PCI1_IDSEL PCI1_REQ64 PCI1_ACK64 Reserved Reserved Reserved MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7 Freescale Semiconductor NOTE Table 67 for the meanings of these notes. Table 68. MPC8547E Pinout Listing Package Pin Number PCI1 (One 64-Bit or One 32-Bit) AB14, AC15, AA15, Y16, W16, AB16, AC16, ...

Page 100

... Supply — — — — 101 — — 2 — — 2 — — 2 — — 2 — — 2 — — 2 — — 2 I/O GV — DD I/O GV — — DD I/O GV — DD I/O GV — — — — — — — — — — Freescale Semiconductor ...

Page 101

... DMA_DREQ[0:1] DMA_DDONE[0:1] UDE MCP MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7 Freescale Semiconductor Package Pin Number Local Bus Controller Interface E27, B20, H19, F25, A20, C19, E28, J23, A25, K22, B28, D27, D19, J22, K20, D28, D25, B25, E22, F22, F21, C25, C22, B23, F20, A23, A22, ...

Page 102

... T10, V7, U10, U5, U4, V6, T5 P2, R2, N1, N2, P3, M2, M1, N3 N9, N10, P8, N7, R9, N5, R8 P10 P7 Power Pin Type Notes Supply I OV — — I I I/O OV — — — — — — — — — — — — — — — — — Freescale Semiconductor ...

Page 103

... TSEC4_TX_EN/TSEC3_TX_ER UART_CTS[0:1] UART_RTS[0:1] UART_SIN[0:1] UART_SOUT[0:1] IIC1_SCL IIC1_SDA IIC2_SCL IIC2_SDA SD_RX[0:3] SD_RX[0:3] SD_TX[0:3] SD_TX[0:3] Reserved Reserved MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7 Freescale Semiconductor Package Pin Number R10 V8, W10, Y10, W7 Y1, W3, W5 V10 V9 AB8, Y7, AA7, Y8 AA1, Y3, AA2, AA4 AA5 Y5 AA3 ...

Page 104

... AE5 AE21 Clock AF16 AH17 JTAG AG28 AH28 AF28 AH27 AH23 Power Pin Type Notes Supply — — 15 — — — — DD — — 2 — — 32 — — 34 — — — — — — — 19 19 — — — Freescale Semiconductor ...

Page 105

... TEST_SEL THERM0 THERM1 ASLEEP GND MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7 Freescale Semiconductor Package Pin Number DFT AC25 AE22 AH20 AH14 Thermal Management AG1 AH1 Power Management AH18 Power and Ground Signals A11, B7, B24, C1, C3, C5, C12, C15, C26, D8, ...

Page 106

... Power for CCB — PLL (1.1 V) Power for — SRDSPLL (1 — — I MVREF Reference voltage signal for DDR 200 Ω GND 100 Ω GND O — 67. Refer to Table 67 for the meanings of these Freescale Semiconductor Notes — — — — — — — 24 ...

Page 107

... PCI1_IDSEL PCI1_REQ64/PCI2_FRAME PCI1_ACK64/PCI2_DEVSEL PCI2_CLK PCI2_IRDY PCI2_PERR MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7 Freescale Semiconductor NOTE Table 67 for the meanings of these notes. Table 69. MPC8545E Pinout Listing Package Pin Number PCI1 and PCI2 (One 64-Bit or Two 32-Bit) AB14, AC15, AA15, Y16, W16, AB16, AC16, ...

Page 108

... K21, C28, B26, B22 H21 Power Pin Type Notes Supply I/O OV — DD I/O OV 2 — DD I/O OV — DD I/O GV — DD I/O GV — — DD I/O GV — DD I/O GV — — — — — — — — — — I/O BV — DD I/O BV — Freescale Semiconductor ...

Page 109

... DMA_DREQ[0:1] DMA_DDONE[0:1] UDE MCP IRQ[0:7] IRQ[8] IRQ[9]/DMA_DREQ3 IRQ[10]/DMA_DACK3 IRQ[11]/DMA_DDONE3 MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7 Freescale Semiconductor Package Pin Number H20, A27, D26, A28 J25, C20, J24, G26, A26 D23 G20 E21 G25 C23 J21 A24 ...

Page 110

... Pin Type Notes Supply I/O OV — — — — — — — — — — 103 — — DD — — 104 — — 104 — — 15 — — 105 I LV 104 DD — — 104 — — 105 — DD Freescale Semiconductor ...

Page 111

... IIC1_SCL IIC1_SDA IIC2_SCL IIC2_SDA SD_RX[0:3] SD_RX[0:3] SD_TX[0:3] SD_TX[0:3] Reserved Reserved Reserved Reserved SD_PLL_TPD SD_REF_CLK SD_REF_CLK MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7 Freescale Semiconductor Package Pin Number V10 V9 AB8, Y7, AA7, Y8 AA1, Y3, AA2, AA4 AA5 Y5 AA3 AB6 DUART AB3, AC5 AC6, AD7 ...

Page 112

... AF3, AF1, AF2 AE5 AE21 Clock AF16 AH17 JTAG AG28 AH28 AF28 AH27 AH23 DFT AC25 AE22 AH20 AH14 Power Pin Type Notes Supply — — 2 — — 32 — — 34 — — — — — — — 19 19 — — — Freescale Semiconductor ...

Page 113

... MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7 Freescale Semiconductor Package Pin Number Thermal Management AG1 AH1 Power Management AH18 Power and Ground Signals A11, B7, B24, C1, C3, C5, C12, C15, C26, D8, D11, D16, D20, D22, E1, E5, E9, E12, E15, E17, F4, F26, G12, G15, G18, G21, G24, H2, ...

Page 114

... PLL (1.1 V) Power for CCB — PLL (1.1 V) Power for — SRDSPLL (1 — — I MVREF Reference voltage signal for DDR 200 Ω GND 100 Ω GND O — 67. Refer to Table 67 for the meanings of these Freescale Semiconductor Notes — — — — — 24 ...

Page 115

... PCI1_CLK PCI1_DEVSEL PCI1_FRAME PCI1_IDSEL cfg_pci1_width Reserved Reserved MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7 Freescale Semiconductor NOTE Table 67 for the meanings of these notes. Table 70. MPC8543E Pinout Listing Package Pin Number PCI1 (One 32-Bit) AB14, AC15, AA15, Y16, W16, AB16, AC16, ...

Page 116

... I/O GV — DD I/O GV — — DD I/O GV — DD I/O GV — — — — — — — — — — Freescale Semiconductor ...

Page 117

... DMA_DREQ[0:1] DMA_DDONE[0:1] UDE MCP MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7 Freescale Semiconductor Package Pin Number E27, B20, H19, F25, A20, C19, E28, J23, A25, E22, F22, F21, C25, C22, B23, F20, A23, A22, E19, A21, D21, F19, B21 K21, C28, B26, B22 ...

Page 118

... Pin Type Notes Supply I OV — — I I I/O OV — — — — — — — — — — 103 — — DD — — 104 — — 104 — — 15 — — 105 I LV 104 DD — — 104 Freescale Semiconductor ...

Page 119

... TSEC3_CRS TSEC3_TX_ER UART_CTS[0:1] UART_RTS[0:1] UART_SIN[0:1] UART_SOUT[0:1] IIC1_SCL IIC1_SDA IIC2_SCL IIC2_SDA SD_RX[0:7] SD_RX[0:7] SD_TX[0:7] SD_TX[0:7] SD_PLL_TPD MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7 Freescale Semiconductor Package Pin Number P10 P7 R10 V8, W10, Y10, W7 Y1, W3, W5 V10 V9 AB8, Y7, AA7, Y8 AA1, Y3, AA2, AA4 AA5 ...

Page 120

... AE5 AE21 Clock AF16 AH17 JTAG AG28 AH28 AF28 AH27 AH23 DFT AC25 AE22 Power Pin Type Notes Supply I XV — — DD — — 2 — — 32 — — 34 — — — — — — — 19 19 — — — Freescale Semiconductor ...

Page 121

... AA24, AA27, AB25, AC28, L21, L23, N22, P20 B3, B11, C7, C9, C14, C17, D4, D6, D10, D15, DD MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7 Freescale Semiconductor Package Pin Number AH20 AH14 Thermal Management AG1 AH1 Power Management AH18 Power and Ground Signals A11, B7, B24, C1, C3, C5, C12, C15, C26, D8, ...

Page 122

... PCI1 PLL (1.1 V) Power for — 26 PCI2 PLL (1.1 V) Power for — 26 e500 PLL (1.1 V) Power for — 26 CCB PLL (1.1 V) Power for — 26 SRDSPLL (1 — — MVREF — Reference voltage signal for DDR 200 Ω (±1%) I — to GND Freescale Semiconductor ...

Page 123

... CCB frequency do not exceed their respective maximum or minimum operating frequencies. Refer to Section 19.2, “CCB/SYSCLK PLL Ratio,” 2.)The minimum e500 core frequency is based on the minimum platform frequency of 333 MHz. MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7 Freescale Semiconductor Package Pin Number AB26 U26 Table 67 ...

Page 124

... Maximum Processor Core Frequency 800, 1000, 1200 MHz Min Max 166 200 and Section 19.3, “e500 Core PLL Ratio,” Unit Notes Max 1000 MHz 1, 2 for ratio settings. Unit Notes MHz 1, 2 for ratio Unit Notes MHz 1, 2 for ratio Freescale Semiconductor ...

Page 125

... Binary Value of LA[28:31] Signals 0000 0001 0010 0011 0100 0101 0110 0111 MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7 Freescale Semiconductor Maximum Processor Core Frequency 800, 1000 MHz Min 166 and Table 77. CCB Clock Ratio CCB:SYSCLK Ratio Binary Value of LA[28:31] Signals 16:1 ...

Page 126

... SYSCLK (MHz) 33.33 41.66 66.66 Platform/CCB Frequency (MHz) 333 400 333 533 375 333 417 400 500 533 Table e500 core:CCB Clock Ratio 2:1 5:2 3:1 7:2 83 100 111 133.33 333 400 333 400 445 533 415 500 500 Freescale Semiconductor 78. ...

Page 127

... Table 81. Package Thermal Characteristics for FC-PBGA Characteristic Die junction-to-ambient (natural convection) Die junction-to-ambient (natural convection) Die junction-to-ambient (200 ft/min) Die junction-to-ambient (200 ft/min) Die junction-to-board MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7 Freescale Semiconductor JEDEC Board Symbol Single-layer board (1s) R θ JA Four-layer board (2s2p) R θ ...

Page 128

... JEDEC Board N/A Section 19.2, “CCB/SYSCLK PLL Ratio.” Section 19.3, “e500 Core PLL Ratio.” _PCI, AV _LBIU, and and preferably these voltages are derived directly from V DD Symbol Value Unit R 0.8 °C/W θ JC _SRDS, respectively). The AV DD Freescale Semiconductor Notes ...

Page 129

... The capacitors are connected from AV the ground plane. Use ceramic chip capacitors with the highest possible self-resonant frequency. All traces should be kept short, wide and direct. MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7 Freescale Semiconductor 150 Ω 2.2 µF 2.2 µF ...

Page 130

... Where the board has blind vias, these capacitors should be placed MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7 130 1 1 2.2 µF 2.2 µF GND Figure 59. SerDes PLL Power Supply Filter . and LV , planes, to enable quick recharging of the _SRDS DD 0.003 µF power plane and and ensure low DD DD Freescale Semiconductor pin ...

Page 131

... When data is held high, SW1 is closed (SW2 is open) and R OV /2. R then becomes the resistance of the pull-up devices other in value. Then MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7 Freescale Semiconductor , C). is trimmed until the voltage at the pad equals P P )/2. N System Design Information ...

Page 132

... MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7 132 Pad Data R P OGND Figure 60. Driver Impedance Measurement Table 82. Impedance Characteristics PCI 43 Target 25 Target 43 Target 25 Target Table 105° SW2 SW1 DDR DRAM Symbol 20 Target Target Z 0 Freescale Semiconductor , DD Unit W W ...

Page 133

... JTAG scan chain is initialized during the power-on reset flow. Freescale recommends that the COP header be designed into the system MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7 Freescale Semiconductor allows the COP port to independently assert HRESET or TRST, Figure ...

Page 134

... No pull-up/pull-down is required for TDI, TMS, TDO, or TCK. COP_RUN/STOP COP_CHKSTP_OUT MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7 134 2 COP_TDO 1 1 COP_TDI COP_TCK 7 8 COP_TMS 9 10 COP_SRESET 11 12 KEY 13 COP_HRESET No pin 15 16 Figure 61. COP Connector Physical Pinout NC COP_TRST COP_VDD_SENSE COP_CHKSTP_IN NC NC GND Freescale Semiconductor ...

Page 135

... This switch is included as a precaution for BSDL testing. The switch should be closed to position A during BSDL testing to avoid accidentally asserting the TRST line. If BSDL testing is not being performed, this switch should be closed to position B. 6. Asserting SRESET causes a machine check interrupt to the e500 core. MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7 Freescale Semiconductor COP_HRESET COP_SRESET B A ...

Page 136

... Reserved pins: T22, T23, M20, M21 The following pins must be connected to GND if not used: • SD_RX[7:0] • SD_RX[7:0] • SD_REF_CLK • SD_REF_CLK MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7 136 NOTE . Pins V27 and M25 must be tied to GND through a 300-Ω DD Freescale Semiconductor ...

Page 137

... For available frequencies, contact your local Freescale sales office. In addition to the processor frequency, the part numbering scheme also MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7 Freescale Semiconductor NOTE . Pins V27 and M25 must be tied to GND through a 300-Ω ...

Page 138

... A = Ver. 2.1 Ver. 2.1.2 (SVR = 0x80390221) Blank = Ver. 2.0 (SVR = 0x80310220 Ver. 2.1 Ver. 2.1.2 (SVR = 0x80310221) Blank = Ver. 2.0 (SVR = 0x803A0020 Ver. 2.1 Ver. 2.1.2 (SVR = 0x803A0021) Blank = Ver. 2.0 (SVR = 0x80320020 Ver. 2.1 Ver. 2.1.2 (SVR = 0x80320021) Freescale Semiconductor ...

Page 139

... CCCCC is the country of assembly. This space is left blank if parts are assembled in the United States. YWWLAZ is assembly traceability code. Figure 63. Part Marking for CBGA and PBGA Device MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7 Freescale Semiconductor Table 83. Part Numbering Nomenclature pp Processor ...

Page 140

... Pinout “MPC8543E Pinout Listing,” added note 5 to LA[28:31]. Table 79, “Frequency Options of SYSCLK with Respect to Memory Bus Speeds.” 2, “Recommended Operating Conditions,” added “Ethernet management” (HSSI),” to reflect that there is only one SerDes. RX-EYE-MEDIAN-to-MAX-JITTER ListingTable 69, “MPC8545E Freescale Semiconductor / .” ...

Page 141

... Figure 58, “PLL Power Supply Filter Circuit with PCI/LBIU Supply Filter Circuit”) into three figures: the original (now specific for AVDD_PCI/AVDD_LBIU) and two new ones. MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7 Freescale Semiconductor Substantive Change(s) Changed platform clock frequency to 4.2. Table 25, changed clock period minimum to 5 ...

Page 142

... Specifications.” and t in Table 40, “Local Bus LBIXKH1 LBIXKH2 Table 40, “Local Bus Timing Parameters , t , and t in Table 42, “Local Bus LBIXKH1 LBIXKL2 and t were previously labeled t LBIXKL2 Enabled)” and Figure 24, “Local Bus and Figure 28. 28. Specifications” Freescale Semiconductor Table 32, LBIVKH2 ...

Page 143

... Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer ...