KMPC8548EVTAUJC Freescale Semiconductor, KMPC8548EVTAUJC Datasheet - Page 132

• Manufacturer Part Number: KMPC8548EVTAUJC
• Manufacturer: Freescale Semiconductor

Specifications of KMPC8548EVTAUJC

• Lead Free Status / Rohs Status: Supplier Unconfirmed

System Design Information
Table 82
nominal OV
21.8
The MPC8548E provides the user with power-on configuration options which can be set through the use
of external pull-up or pull-down resistors of 4.7 kΩ on certain output pins (see customer visible
configuration pins). These pins are generally used as output only pins in normal operation.
While HRESET is asserted however, these pins are treated as inputs. The value presented on these pins
while HRESET is asserted, is latched when HRESET deasserts, at which time the input receiver is disabled
and the I/O circuit takes on its normal function. Most of these sampled configuration pins are equipped
with an on-chip gated resistor of approximately 20 kΩ. This value should permit the 4.7-kΩ resistor to pull
the configuration pin to a valid logic low level. The pull-up resistor is enabled only during HRESET (and
for platform/system clocks after HRESET deassertion to ensure capture of the reset value). When the input
receiver is disabled the pull-up is also, thus allowing functional operation of the pin as an output with
minimal signal quality or delay disruption. The default value for all configuration bits treated this way has
been encoded such that a high voltage level puts the device into the default state and external resistors are
needed only when non-default settings are required by the user.
Careful board layout with stubless connections to these pull-down resistors coupled with the large value
of the pull-down resistor should minimize the disruption of signal quality or speed for output pins thus
configured.
132
Note: Nominal supply voltages. See
Impedance
R
R
summarizes the signal impedance targets. The driver impedances are targeted at minimum V
N
P
Configuration Pin Muxing
DD
, 105°C.
MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7
Local Bus, Ethernet, DUART, Control,
Configuration, Power Management
43 Target
43 Target
Figure 60. Driver Impedance Measurement
Table
Data
Table 82. Impedance Characteristics
1, T
j
= 105°C.
25 Target
25 Target
PCI
Pad
R
R
OGND
OV
N
P
DD
SW2
SW1
DDR DRAM
20 Target
20 Target
Freescale Semiconductor
Symbol
Z
Z
0
0
Unit
W
W
DD
,