DS21554LB+ Maxim Integrated Products, DS21554LB+ Datasheet - Page 46

• Manufacturer Part Number: DS21554LB+
• Description: IC TXRX E1 5V 100-LQFP
• Manufacturer: Maxim Integrated Products

Specifications of DS21554LB+

• Function: Single-Chip Transceiver
• Interface: E1, HDLC, J1, T1
• Number Of Circuits: 1
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 75mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Includes: Remote and AIS Alarm Detector / Generator
• Product: Framer
• Number Of Transceivers: 1
• Data Rate: 1.544 Mbps
• Supply Voltage (max): 5.25 V
• Supply Voltage (min): 4.75 V
• Supply Current (max): 75 mA (Typ)
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Ic Interface Type: Parallel, Serial
• Supply Voltage Range: 4.75V To 5.25V
• Operating Temperature Range: 0°C To +70°C
• Digital Ic Case Style: LQFP
• No. Of Pins: 100
• Filter Terminals: SMD
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power (watts): -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Table 6-1. Alarm Criteria
(Receive Remote Alarm)
(Receive Unframed All
(Receive Signaling All
(Receive Signaling All
(Receive Carrier Loss)
Multiframe Alarm)
(Receive Distant
ALARM
RDMA
Zeros)
RUA1
RSA1
RSA0
Ones)
Ones)
RRA
RCL
over 16 consecutive frames
(one full MF) time slot 16
contains less than three
zeros
over 16 consecutive frames
(one full MF) time slot 16
contains all zeros
bit 6 in time slot 16 of
frame 0 set to one for two
consecutive MF
less than three zeros in two
frames (512–bits)
bit 3 of non-align frame set
to one for three
consecutive occasions
255 (or 2048) consecutive
zeros received
SET CRITERIA
46 of 124
over 16 consecutive frames
(one full MF) time slot 16
contains three or more
zeros
over 16 consecutive frames
(one full MF) time slot 16
contains at least a single
one
bit 6 in time slot 16 of
frame 0 set to zero for two
consecutive MF
more than two zeros in two
frames (512 bits)
bit 3 of non-align frame set
to zero for three
consecutive occasions
in 255-bit times, at least 32
ones are received
CLEAR CRITERIA
G.775 / G.962
ITU SPEC.
1.6.1.2
G.732
G.732
O.162
O.162
O.162
2.1.5
2.1.4
4.2
5.2