DS2155L Maxim Integrated Products, DS2155L Datasheet - Page 106

• Manufacturer Part Number: DS2155L
• Description: IC TXRX T1/E1/J1 1-CHIP 100-LQFP
• Manufacturer: Maxim Integrated Products

Specifications of DS2155L

• Function: Single-Chip Transceiver
• Interface: E1, HDLC, J1, T1
• Number Of Circuits: 1
• Voltage - Supply: 3.14 V ~ 3.47 V
• Current - Supply: 75mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Includes: BERT Generator and Detector, CMI Coder and Decoder, HDLC Controller
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Power (watts): -

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 0/Receive Elastic Store Slip-Occurrence Event (RSLIP). Set when the receive elastic store has either
repeated or deleted a frame.
Bit 1/Receive Elastic Store Empty Event (RESEM). Set when the receive elastic store buffer empties and a
frame is repeated.
Bit 2/Receive Elastic Store Full Event (RESF). Set when the receive elastic store buffer fills and a frame is
deleted.
Bit 3/Transmit Elastic Store Slip-Occurrence Event (TSLIP). Set when the transmit elastic store has either
repeated or deleted a frame.
Bit 4/Transmit Elastic Store Empty Event (TESEM). Set when the transmit elastic store buffer empties and a
frame is repeated.
Bit 5/Transmit Elastic Store Full Event (TESF). Set when the transmit elastic store buffer fills and a frame is
deleted.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 0/Receive Elastic Store Slip-Occurrence Event (RSLIP)
Bit 1/Receive Elastic Store Empty Event (RESEM)
Bit 2/Receive Elastic Store Full Event (RESF)
Bit 3/Transmit Elastic Store Slip-Occurrence Event (TSLIP)
Bit 4/Transmit Elastic Store Empty Event (TESEM)
Bit 5/Transmit Elastic Store Full Event (TESF)
0 = interrupt masked
1 = interrupt enabled
0 = interrupt masked
1 = interrupt enabled
0 = interrupt masked
1 = interrupt enabled
0 = interrupt masked
1 = interrupt enabled
0 = interrupt masked
1 = interrupt enabled
0 = interrupt masked
1 = interrupt enabled
—
—
7
7
0
0
—
—
SR5
Status Register 5
1Eh
IMR5
Interrupt Mask Register 5
1Fh
6
0
6
0
TESF
TESF
5
0
5
0
TESEM
TESEM
4
0
4
0
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TSLIP
TSLIP
3
0
3
0
RESF
RESF
2
0
2
0
RESEM
RESEM
1
0
1
0
RSLIP
RSLIP
0
0
0
0