DS21352L Maxim Integrated Products, DS21352L Datasheet - Page 71
DS21352L
Manufacturer Part Number
DS21352L
Description
IC TXRX T1 1-CHIP 3.3V 100-LQFP
Manufacturer
Maxim Integrated Products
Datasheet
1.DS21352L.pdf
(137 pages)
Specifications of DS21352L
Function
Single-Chip Transceiver
Interface
HDLC, T1
Number Of Circuits
1
Voltage - Supply
3.14 V ~ 3.47 V
Current - Supply
75mA
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
100-LQFP
Includes
DSX-1 and CSU Line Build-Out Generator, HDLC Controller, In-Band Loop Code Generator and Detector
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Power (watts)
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DS21352L
Manufacturer:
JRC
Quantity:
5 510
Part Number:
DS21352L
Manufacturer:
DALLAS
Quantity:
20 000
Company:
Part Number:
DS21352LN+
Manufacturer:
Maxim Integrated Products
Quantity:
135
NOTE:
The RBOC, RPE, RPS, and TMEND bits are latched and will be cleared when read.
TMEND
RHALF
THALF
RNE
RPE
TNF
RPS
HSR.6
HSR.5
HSR.4
HSR.3
HSR.2
HSR.1
HSR.0
Receive Packet End. Set when the HDLC controller detects either the finish of a valid
message (i.e., CRC check complete) or when the controller has experienced a message
fault such as a CRC checking error, or an overrun condition, or an abort has been seen.
The setting of this bit prompts the user to read the RPRM register for details.
Receive Packet Start. Set when the HDLC controller detects an opening byte. The
setting of this bit prompts the user to read the RPRM register for details.
Receive FIFO Half Full. Set when the receive 64–byte FIFO fills beyond the half way
point. The setting of this bit prompts the user to read the RPRM register for details.
Receive FIFO Not Empty. Set when the receive 64–byte FIFO has at least one byte
available for a read. The setting of this bit prompts the user to read the RPRM register
for details.
Transmit FIFO Half Empty. Set when the transmit 64–byte FIFO empties beyond the
half way point. The setting of this bit prompts the user to read the TPRM register for
details.
Transmit FIFO Not Full. Set when the transmit 64–byte FIFO has at least one byte
available. The setting of this bit prompts the user to read the TPRM register for details.
Transmit Message End. Set when the transmit HDLC controller has finished sending a
message. The setting of this bit prompts the user to read the TPRM register for details.
71 of 137