SC16C554BIBM,151 NXP Semiconductors, SC16C554BIBM,151 Datasheet - Page 32

• Manufacturer Part Number: SC16C554BIBM,151
• Description: IC UART QUAD W/FIFO 64-LQFP
• Manufacturer: NXP Semiconductors

Specifications of SC16C554BIBM,151

• Number Of Channels: 4, QUART
• Fifo's: 16 Byte
• Voltage - Supply: 2.5V, 3.3V, 5V
• With Auto Flow Control: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• With Cmos: Yes
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-3267; 935279067151; SC16C554BIBM-S

NXP Semiconductors
SC16C554B_554DB
Product data sheet
7.5 Line Control Register (LCR)
The Line Control Register is used to specify the asynchronous data communication
format. The word length, the number of stop bits, and the parity are selected by writing the
appropriate bits in this register.
Table 15.
Bit
7
6
5
4
3
2
1:0
Symbol
LCR[7]
LCR[6]
LCR[5]
LCR[4]
LCR[3]
LCR[2]
LCR[1:0]
Line Control Register bits description
All information provided in this document is subject to legal disclaimers.
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs
Description
Divisor latch enable. The internal baud rate counter latch and Enhance
Feature mode enable.
Set break. When enabled, the Break control bit causes a break condition to
be transmitted (the TX output is forced to a logic 0 state). This condition
exists until disabled by setting LCR[6] to a logic 0.
Set parity. If the parity bit is enabled, LCR[5] selects the forced parity format.
Programs the parity conditions (see
Even parity. If the parity bit is enabled with LCR[3] set to a logic 1, LCR[4]
selects the even or odd parity format.
Parity enable. Parity or no parity can be selected via this bit.
Stop bits. The length of stop bit is specified by this bit in conjunction with the
programmed word length (see
Word length bits 1, 0. These two bits specify the word length to be
transmitted or received (see
logic 0 = divisor latch disabled (normal default condition)
logic 1 = divisor latch enabled
logic 0 = no TX break condition (normal default condition)
logic 1 = forces the transmitter output (TX) to a logic 0 for alerting the
remote receiver to a line break condition
logic 0 = parity is not forced (normal default condition)
LCR[5] = logic 1 and LCR[4] = logic 0: parity bit is forced to a logic 1 for the
transmit and receive data
LCR[5] = logic 1 and LCR[4] = logic 1: parity bit is forced to a logic 0 for the
transmit and receive data
logic 0 = odd parity is generated by forcing an odd number of logic 1s in
the transmitted data. The receiver must be programmed to check the same
format (normal default condition).
logic 1 = even parity is generated by forcing an even number of logic 1s in
the transmitted data. The receiver must be programmed to check the same
format.
logic 0 = no parity (normal default condition)
logic 1 = a parity bit is generated during the transmission, receiver checks
the data and parity for transmission errors
logic 0 or cleared = default condition
logic 0 or cleared = default condition
Rev. 4 — 8 June 2010
Table
Table
SC16C554B/554DB
18).
Table
17).
16).
© NXP B.V. 2010. All rights reserved.
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