AT32UC3A1256AU Atmel Corporation, AT32UC3A1256AU Datasheet - Page 506

• Manufacturer Part Number: AT32UC3A1256AU
• Manufacturer: Atmel Corporation

Specifications of AT32UC3A1256AU

• Flash (kbytes): 256 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 69
• Ext Interrupts: 69
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device + OTG
• Spi: 6
• Twi (i2c): 1
• Uart: 4
• Ssc: 1
• Ethernet: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 16
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0-3.6 or (1.65-1.95+3.0-3.6)
• Operating Voltage (vcc): 3.0-3.6 or (1.65-1.95+3.0-3.6)
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 10
• Output Compare Channels: 16
• Input Capture Channels: 6
• Pwm Channels: 13
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

32058K AVR32-01/12
30.7.1.4.6
30.7.1.5
30.7.1.5.1
Figure 30-7. Speed Selection in Device Mode
30.7.1.5.2
30.7.1.6
USB Suspend mode :
Speed Control
DPRAM Management
Device Mode
Host Mode
In peripheral mode, the UDINT.SUSP bit indicates that the usb line is in the suspend mode. In
this case, the USB Data transceiver is automatically set in suspend mode to reduce the
consumption.
When the USB interface is in device mode, the speed selection (full-/low-speed) depends on
which of D+ and D- is pulled up. The LS bit allows to connect an internal pull-up resistor either
on D+ (full-speed mode) or on D- (low-speed mode). The LS bit should be configured before
attaching the device, what can be done by clearing the DETACH bit.
When the USB interface is in host mode, internal pull-down resistors are connected on both D+
and D- and the interface detects the speed of the connected device, which is reflected by the
SPEED bit-field.
Pipes and endpoints can only be allocated in ascending order (from the pipe/endpoint 0 to the
last pipe/endpoint to be allocated). The firmware shall therefore configure them in the same
order.
The allocation of a pipe/endpoint k
cates a memory area in the DPRAM and inserts it between the k
k
point memory windows (from k
i+1
•the VBus Transition interrupt (VBUSTI);
•the Wake-Up interrupt (WAKEUP);
•the Host Wake-Up interrupt (HWUPI).
pipe/endpoint memory window slides up and its data is lost. Note that the following pipe/end-
VBUS
D+
D-
i+2
) do not slide.
i
starts when its ALLOC bit is set. Then, the hardware allo-
UDCON.DETACH
UDCON.LS
i-1
and k
i+1
pipes/endpoints. The
AT32UC3A
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