AT32UC3A1256AU Atmel Corporation, AT32UC3A1256AU Datasheet - Page 749

• Manufacturer Part Number: AT32UC3A1256AU
• Manufacturer: Atmel Corporation

Specifications of AT32UC3A1256AU

• Flash (kbytes): 256 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 69
• Ext Interrupts: 69
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device + OTG
• Spi: 6
• Twi (i2c): 1
• Uart: 4
• Ssc: 1
• Ethernet: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 16
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0-3.6 or (1.65-1.95+3.0-3.6)
• Operating Voltage (vcc): 3.0-3.6 or (1.65-1.95+3.0-3.6)
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 10
• Output Compare Channels: 16
• Input Capture Channels: 6
• Pwm Channels: 13
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

32058K AVR32-01/12
36.8
36.8.1
36.8.2
36.8.3
36.8.4
Public JTAG instructions
IDCODE
SAMPLE_PRELOAD
EXTEST
INTEST
For description of what memory locations remain accessible, please refer to the SAB address
map.
Full access to these instructions is re-enabled when the security fuse is erased by the
CHIP_ERASE JTAG instruction.
Note that the security bit will read as programmed and block these instructions also if the Flash
Controller is statically reset.
Other security mechanisms can also restrict these functions. If such mechanisms are present
they are listed in the SAB address map section.
This instruction selects the 32 bit ID register as Data Register. The ID register consists of a ver-
sion number, a device number and the manufacturer code chosen by JEDEC. This is the default
instruction after power-up.
The active states are:
JTAG instruction for taking a snap-shot of the input/output pins without affecting the system
operation, and pre-loading the scan chain without updating the DR-latch. The Boundary-Scan
Chain is selected as Data Register.
The active states are:
JTAG instruction for selecting the Boundary-Scan Chain as Data Register for testing circuitry
external to the AVR32 package. The contents of the latched outputs of the Boundary-Scan chain
is driven out as soon as the JTAG IR-register is loaded with the EXTEST instruction.
The active states are:
This instruction selects the Boundary-Scan Chain as Data Register for testing internal logic in
the device. The logic inputs are determined by the Boundary-Scan Chain, and the logic outputs
are captured by the Boundary-Scan chain. The device output pins are driven from the Boundary-
Scan Chain.
The active states are:
• Capture-DR: The static IDCODE value is latched into the shift register.
• Shift-DR: The IDCODE scan chain is shifted by the TCK input.
• Capture-DR: Data on the external pins are sampled into the Boundary-Scan Chain.
• Shift-DR: The Boundary-Scan Chain is shifted by the TCK input.
• Capture-DR: Data on the external pins is sampled into the Boundary-Scan Chain.
• Shift-DR: The Internal Scan Chain is shifted by the TCK input.
• Update-DR: Data from the scan chain is applied to output pins.
• Capture-DR: Data from the internal logic is sampled into the Boundary-Scan Chain.
AT32UC3A
749