AT90CAN128 Automotive Atmel Corporation, AT90CAN128 Automotive Datasheet - Page 32
AT90CAN128 Automotive
Manufacturer Part Number
AT90CAN128 Automotive
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT90CAN128_AUTOMOTIVE.pdf
(431 pages)
2.AT90CAN128_AUTOMOTIVE.pdf
(16 pages)
3.AT90CAN128_AUTOMOTIVE.pdf
(225 pages)
Specifications of AT90CAN128 Automotive
Flash (kbytes)
128 Kbytes
Pin Count
64
Max. Operating Frequency
16 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
53
Ext Interrupts
8
Usb Speed
No
Usb Interface
No
Spi
1
Twi (i2c)
1
Uart
2
Can
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
4
Eeprom (bytes)
4096
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 125
I/o Supply Class
2.7 to 5.5
Operating Voltage (vcc)
2.7 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
4
Output Compare Channels
8
Input Capture Channels
2
Pwm Channels
7
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
- AT90CAN128_AUTOMOTIVE PDF datasheet
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- AT90CAN128_AUTOMOTIVE PDF datasheet #3
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- Download datasheet (6Mb)
4.5.6
32
AT90CAN32/64/128
External Memory Control Register A – XMCRA
• Bit 7 – SRE: External SRAM/XMEM Enable
Writing SRE to one enables the External Memory Interface.The pin functions AD7:0, A15:8,
ALE, WR, and RD are activated as the alternate pin functions. The SRE bit overrides any pin
direction settings in the respective data direction registers. Writing SRE to zero, disables the
External Memory Interface and the normal pin and data direction settings are used. Note that
when the XMEM interface is disabled, the address space above the internal SRAM boundary is
not mapped into the internal SRAM.
• Bit 6..4 – SRL2, SRL1, SRL0: Wait-state Sector Limit
It is possible to configure different wait-states for different External Memory addresses. The
external memory address space can be divided in two sectors that have separate wait-state bits.
The SRL2, SRL1, and SRL0 bits select the split of the sectors, see
default, the SRL2, SRL1, and SRL0 bits are set to zero and the entire external memory address
space is treated as one sector. When the entire SRAM address space is configured as one sec-
tor, the wait-states are configured by the SRW11 and SRW10 bits.
Table 4-3.
Note:
Bit
Read/Write
Initial Value
SRL2
0
0
0
0
1
1
1
1
1. See
Sector limits with different settings of SRL2..0
SRE
R/W
Table 4-1 on page 18
7
0
SRL1
0
0
1
1
0
0
1
1
SRL2
R/W
6
0
SRL0
SRL1
R/W
5
0
0
1
0
1
0
1
0
1
for “XMem start” setting.
SRL0
R/W
4
0
Lower sector
Upper sector
Lower sector
Upper sector
Lower sector
Upper sector
Lower sector
Upper sector
Lower sector
Upper sector
Lower sector
Upper sector
Lower sector
Upper sector
Lower sector
Upper sector
SRW11
R/W
Sector
3
0
SRW10
R/W
2
0
SRW01
R/W
1
0
Table 4-3
“XMem start”
“XMem start”
“XMem start”
“XMem start”
“XMem start”
“XMem start”
“XMem start”
“XMem start”
SRW00
R/W
0
0
Addressing
0xC000 - 0xFFFF
0xA000 - 0xFFFF
0xE000 - 0xFFFF
0x2000 - 0xFFFF
0x4000 - 0xFFFF
0x6000 - 0xFFFF
0x8000 - 0xFFFF
and
N/A
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
XMCRA
7682C–AUTO–04/08
Figure
- 0xDFFF
- 0xBFFF
- 0xFFFF
- 0x1FFF
- 0x3FFF
- 0x5FFF
- 0x7FFF
- 0x9FFF
4-4. By
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