ATxmega64A1 Atmel Corporation, ATxmega64A1 Datasheet - Page 155

• Manufacturer Part Number: ATxmega64A1
• Manufacturer: Atmel Corporation

Specifications of ATxmega64A1

• Flash (kbytes): 64 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 78
• Ext Interrupts: 78
• Usb Speed: No
• Usb Interface: No
• Spi: 12
• Twi (i2c): 4
• Uart: 8
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 4
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 4
• Eeprom (bytes): 2048
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 8
• Output Compare Channels: 24
• Input Capture Channels: 24
• Pwm Channels: 24
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

14.6.1
14.6.2
14.6.3
14.6.4
8077H–AVR–12/09
Normal Operation
Event Action Controlled Operation
32-bit Operation
Changing the Period
In Normal Operation the Counter will count in the direction set by the Direction (DIR) bit for each
clock until it reaches TOP or BOTTOM. When TOP is reached when up-counting, the counter
will be set to zero when the next clock is given. When down-counting the Counter is reloaded
with Period Register value when BOTTOM is reached.
Figure 14-6. Normal Mode of Operation
As shown in
write access has higher priority than count, clear, or reload and will be immediate. The direction
of the Counter can also be changed during normal operation.
Normal operation must be used when using the counter as timer base for the capture channels.
The Event Selection and Event Action settings can be used to control the Counter from the
Event System. For the Counter the event actions can be selected to:
Two Timer/Counters can be used together to enable 32-bit counter operation. By using two
Timer/Counters the overflow event from one Timer/Counter (least significant timer) can be
routed via the Event System and used as clock input for another Timer/Counter (most significant
timer).
The Counter period is changed by writing a new TOP value to the Period Register. If double
buffering is not used, any period update is immediate as shown in
• Event system controlled Up/Down counting.
• Event system controlled Quadrature Decode counting.
CNT
DIR
MAX
Figure 14-6
TOP
BOT
changing the counter value while the counter is running is possible. The
CNT written
Figure 14-7 on page
XMEGA A
"update"
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