ATxmega64A1 Atmel Corporation, ATxmega64A1 Datasheet - Page 358

• Manufacturer Part Number: ATxmega64A1
• Manufacturer: Atmel Corporation

Specifications of ATxmega64A1

• Flash (kbytes): 64 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 78
• Ext Interrupts: 78
• Usb Speed: No
• Usb Interface: No
• Spi: 12
• Twi (i2c): 4
• Uart: 8
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 4
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 4
• Eeprom (bytes): 2048
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 8
• Output Compare Channels: 24
• Input Capture Channels: 24
• Pwm Channels: 24
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

29.6.3
29.6.4
8077H–AVR–12/09
Repeat Counter Register
Operand Count Register
itself. Indirect data access can be optionally combined with pointer register post-increment. The
indirect access mode has an option that makes it possible to load or read the pointer register
without accessing any other registers. Any register update is performed in a little-endian fashion.
Hence, loading a single byte of the address register will always update the LSB byte while the
MSB bytes are left unchanged.
The Pointer Register is not involved in addressing registers in the PDI Control and Status Regis-
ter Space (CSRS space).
The REPEAT instruction will always be accompanied by one or more operand bytes that define
the number of times the next instruction should be repeated. These operand bytes are copied
into the Repeat Counter register upon reception. During the repeated executions of the instruc-
tion following immediately after the REPEAT instruction and its operands, the Repeat Counter
register is decremented until it reaches zero, indicating that all repetitions are completed. The
repeat counter is also involved in key reception.
Immediately after and instruction (except the LDCS and the STCS instructions) a specified num-
ber of operands or data bytes (given by the size parts of the instruction) are expected. The
operand count register is used to keep track of how many bytes that have been transferred.
XMEGA A
358