M42800A Atmel Corporation, M42800A Datasheet - Page 222

• Manufacturer Part Number: M42800A
• Manufacturer: Atmel Corporation

Specifications of M42800A

• Flash (kbytes): 0 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 33 MHz
• Cpu: ARM7TDMI
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 54
• Ext Interrupts: 54
• Usb Speed: No
• Usb Interface: No
• Spi: 2
• Uart: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 8
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.3/5.0
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Debug in Depth
B-4
Scan chain 0
Scan chain 0 enables access to the entire periphery of the ARM7TDMI core, including
the data bus. The scan chain functions enable inter-device testing (EXTEST) and serial
testing of the core (INTEST). The order of the scan chain, from search data in to out, is:
1.
2.
3.
Scan chain 1
Scan chain 1 is a subset of scan chain 0. It provides serial access to the core data bus
D[31:0] and the BREAKPT signal.
There are 33 bits in this scan chain, the order from serial data in to serial data out, is:
1.
2.
Scan chain 2
Scan chain 2 enables access to the EmbeddedICE Logic registers. Refer to Test data
registers on page B-14 for details.
Data bus bits 0 to 31.
The control signals.
Address bus bits 31 to 0.
A[0] is scanned out first.
Data bus bits 0 to 31.
The BREAKPT bit, the first to be shifted out.
Embedded-ICE
Copyright © 1994-2001. All rights reserved.
Scan chain 2
Logic
Scan chain 0
Figure B-1 ARM7TDMI core scan chain arrangements
Scan chain 1
TAP controller
ARM7TDM
(CPU core)
ARM DDI 0029G