M42800A Atmel Corporation, M42800A Datasheet - Page 9
M42800A
Manufacturer Part Number
M42800A
Description
Manufacturer
Atmel Corporation
Datasheets
1.M40800.pdf
(284 pages)
2.M40800.pdf
(153 pages)
3.M42800A.pdf
(224 pages)
4.M42800A.pdf
(27 pages)
Specifications of M42800A
Flash (kbytes)
0 Kbytes
Pin Count
144
Max. Operating Frequency
33 MHz
Cpu
ARM7TDMI
Hardware Qtouch Acquisition
No
Max I/o Pins
54
Ext Interrupts
54
Usb Speed
No
Usb Interface
No
Spi
2
Uart
2
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
8
Self Program Memory
NO
External Bus Interface
1
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.3/5.0
Fpu
No
Mpu / Mmu
no / no
Timers
6
Output Compare Channels
6
Input Capture Channels
6
32khz Rtc
Yes
Calibrated Rc Oscillator
No
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List of Tables
ARM7TDMI Technical Reference Manual
ARM DDI 0029G
Table 1-1
Table 1-2
Table 1-3
Table 1-4
Table 1-5
Table 1-6
Table 1-7
Table 2-1
Table 2-2
Table 2-3
Table 2-4
Table 2-5
Table 3-1
Table 3-2
Table 3-3
Table 3-4
Table 3-5
Table 3-6
Table 3-7
Table 3-8
Table 4-1
Table 4-2
Change history .............................................................................................................. ii
Key to tables ........................................................................................................... 1-10
ARM instruction summary ....................................................................................... 1-12
Addressing modes .................................................................................................. 1-15
Operand 2 ............................................................................................................... 1-18
Fields ....................................................................................................................... 1-18
Condition fields ........................................................................................................ 1-19
Thumb instruction set summary .............................................................................. 1-21
Register mode identifiers .......................................................................................... 2-7
PSR mode bit values ............................................................................................... 2-15
Exception entry and exit .......................................................................................... 2-16
Exception vectors .................................................................................................... 2-21
Exception priority order ........................................................................................... 2-22
Bus cycle types ......................................................................................................... 3-5
Burst types ................................................................................................................ 3-7
Significant address bits ........................................................................................... 3-12
nOPC ...................................................................................................................... 3-12
nTRANS encoding .................................................................................................. 3-13
Tristate control of processor outputs ....................................................................... 3-21
Read accesses ........................................................................................................ 3-27
Use of nM[4:0] to indicate current processor mode ................................................ 3-32
Coprocessor availability ............................................................................................ 4-3
Handshaking signals ................................................................................................. 4-6
Copyright © 1994-2001. All rights reserved.
ix
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