AD7356 Analog Devices, AD7356 Datasheet - Page 7

• Manufacturer Part Number: AD7356
• Description: Differential Input, Dual, Simultaneous Sampling, 5 MSPS, 12-Bit, SAR ADC
• Manufacturer: Analog Devices

Specifications of AD7356

• Resolution (bits): 12bit
• # Chan: 2
• Sample Rate: 5MSPS
• Interface: Ser,SPI
• Analog Input Type: Diff-Uni
• Ain Range: (Vref) p-p,2.048 V p-p
• Adc Architecture: SAR
• Pkg Type: SOP

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Table 5. Pin Function Descriptions
Pin No.
1, 2
3, 6
4
5, 11
7, 8
9
10
12
13, 14
15
16
Mnemonic
V
REF
REFGND
AGND
V
V
CS
DGND
SDATA
SCLK
V
INA+
INB−
DD
DRIVE
A
, V
, V
, REF
INB+
B
INA−
, SDATA
B
A
Description
Analog Inputs of ADC A. These analog inputs form a fully differential pair.
Reference Decoupling Capacitor Pins. Decoupling capacitors are connected between these pins and the
REFGND pin to decouple the reference buffer for each respective ADC. It is recommended to decouple each
reference pin with a 10 μF capacitor. Provided the output is buffered, the on-chip reference can be taken from
these pins and applied externally to the rest of the system. The nominal internal reference voltage is 2.048 V
and appears at these pins. These pins can also be overdriven by an external reference. The input voltage range
for the external reference is 2.048 V + 100 mV to V
Reference Ground. This is the ground reference point for the reference circuitry on the AD7356. Refer any
external reference signal to this REFGND voltage. Decoupling capacitors must be placed between this pin and
the REF
Analog Ground. This is the ground reference point for all analog circuitry on the AD7356. All analog input
signals should be referred to this AGND voltage. The AGND and DGND voltages should ideally be at the same
potential and must not be more than 0.3 V apart, even on a transient basis.
Analog Inputs of ADC B. These analog inputs form a fully differential pair.
Power Supply Input. The V
capacitor in parallel with a 10 μF tantalum capacitor.
Chip Select. Active low logic input. This input provides the dual functions of initiating conversions on the
AD7356 and framing the serial data transfer.
Digital Ground. This is the ground reference point for all digital circuitry on the AD7356. Connect this pin to
the DGND plane of a system. The DGND and AGND voltages should ideally be at the same potential and must
not be more than 0.3 V apart, even on a transient basis.
Serial Data Outputs. The data output is supplied to each pin as a serial data stream. The bits are clocked out
on the falling edge of the SCLK input. To access the 12 bits of data from the AD7356, 14 SCLK falling edges are
required. The data simultaneously appears on both data output pins from the simultaneous conversions of
both ADCs. The data stream consists of two leading zeros followed by the 12 bits of conversion data. The data
is provided MSB first. If CS is held low for 16 SCLK cycles rather than 14 on the AD7356, then two trailing zeros
appear after the 12 bits of data. If CS is held low for a further 16 SCLK cycles on either SDATA or SDATA
data from the other ADC follows on the SDATA pins. This allows data from a simultaneous conversion on both
ADCs to be gathered in serial format on either SDATA
Serial Clock. Logic input. A serial clock input provides the serial clock for accessing the data from the AD7356.
This clock is also used as the clock source for the conversion process.
Logic Power Supply Input. The voltage supplied at this pin determines at what voltage the interface operates.
The voltage at this pin may be different than the voltage at V
DGND with a 0.1 μF capacitor in parallel with a 10 μF tantalum capacitor.
A
and REF
B
pins. Connect the REFGND pin to the AGND plane of a system.
REFGND
AGND
V
REF
REF
V
V
V
DD
INA+
INA–
INB–
INB+
A
B
range for the AD7356 is 2.5 V ± 10%. Decouple the supply to AGND with a 0.1 μF
Figure 2. Pin Configuration
1
3
4
5
6
8
2
7
Rev. A | Page 7 of 20
(Not to Scale)
AD7356
TOP VIEW
16
15
14
13
12
11
10
9
V
SCLK
SDATA
SDATA
DGND
AGND
CS
V
DD
DRIVE
DD
.
A
or SDATA
A
B
DD
. The V
B
.
DRIVE
supply should be decoupled to
A
AD7356
B
, the