AD7938 Analog Devices, AD7938 Datasheet - Page 28

• Manufacturer Part Number: AD7938
• Description: 8-Channel, 1.5 MSPS, 12-Bit Parallel ADCs with a Sequencer
• Manufacturer: Analog Devices

Specifications of AD7938

• Resolution (bits): 12bit
• # Chan: 8
• Sample Rate: 1.5MSPS
• Interface: Byte,Par
• Analog Input Type: Diff-Uni,SE-Uni
• Ain Range: (2Vref) p-p,5V p-p,Uni (Vref),Uni (Vref) x 2,Uni 2.5V,Uni 5.0V
• Adc Architecture: SAR
• Pkg Type: CSP,QFP

AD7938/AD7939
POWER MODES OF OPERATION
The AD7938/AD7939 have four different power modes of
operation. These modes are designed to provide flexible power
management options. Different options can be chosen to
optimize the power dissipation/throughput rate ratio for
differing applications. The mode of operation is selected by the
power management bits, PM1 and PM0, in the control register,
as detailed in Table 9. When power is first applied to the
AD7938/AD7939, an on-chip, power-on reset circuit ensures
that the default power-up condition is normal mode.
Note that, after power-on, the track-and-hold is in hold mode
and the first rising edge of CONVST places the track-and-hold
into track mode.
Normal Mode (PM1 = PM0 = 0)
This mode is intended for the fastest throughput rate
performance because the user does not have to worry about any
power-up times associated with the AD7938/AD7939. It
remains fully powered up at all times. At power-on reset, this
mode is the default setting in the control register.
Autoshutdown (PM1 = 0; PM0 = 1)
In this mode of operation, the AD7938/AD7939 automatically
enter full shutdown at the end of each conversion, which is
shown at Point A in Figure 36 and Figure 40. In shutdown
mode, all internal circuitry on the device is powered down.
The parts retain information in the control register during
shutdown. The track-and-hold also goes into hold at this point
and remains in hold as long as the device is in shutdown. The
AD7938/AD7939 remains in shutdown mode until the next
rising edge of CONVST (see Point B in Figure 36 or Figure 40).
In order to keep the device in shutdown for as long as possible,
CONVST should idle low between conversions, as shown in
Figure 40. On this rising edge, the part begins to power-up and
the track-and-hold returns to track mode. The power-up time
required is 10 ms minimum regardless of whether the user is
operating with the internal or external reference. The user
should ensure that the power-up time has elapsed before
initiating a conversion.
CONVST
CLKIN
BUSY
1
A
Figure 40. Autoshutdown/Autostandby Mode
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Autostandby (PM1 = 1; PM0 = 0)
In this mode of operation, the AD7938/AD7939 automatically
enter standby mode at the end of each conversion, which is
shown as Point A in Figure 36. When this mode is entered, all
circuitry on the AD7938/AD7939 is powered down except for
the reference and reference buffer. The track-and-hold goes into
hold at this point also and remains in hold as long as the device
is in standby. The parts remain in standby until the next rising
edge of CONVST powers up the device. The power-up time
required depends on whether the internal or external reference
is used. With an external reference, the power-up time required
is a minimum of 600 ns, while when using the internal
reference, the power-up time required is a minimum of 7 μs.
The user should ensure this power-up time has elapsed before
initiating another conversion as shown in Figure 40. This
rising edge of CONVST also places the track-and-hold back
into track mode.
Full Shutdown Mode (PM1 =1; PM0 = 1)
When this mode is programmed, all circuitry on the
AD7938/AD7939 is powered down upon completion of the
write operation, that is, on the rising edge of WR . The track-
and-hold enters hold mode at this point. The parts retain
the information in the control register while the part is in
shutdown. The AD7938/AD7939 remain in full shutdown
mode, with the track-and-hold in hold mode, until the power
management bits (PM1 and PM0) in the control register are
changed. If a write to the control register occurs while the part
is in full shutdown mode, and the power management bits are
changed to PM0 = PM1 = 0 (normal mode), the part begins to
power up on the WR rising edge and the track-and-hold returns
to track. To ensure the part is fully powered up before a conversion
is initiated, the power-up time of 10 ms minimum should be
allowed before the next CONVST falling edge; otherwise,
invalid data is read.
Note that all power-up times quoted apply with a 470 nF
capacitor on the V
B
t
POWER-UP
REFIN
pin.
1
14
Data Sheet