AD9772A Analog Devices, AD9772A Datasheet
AD9772A
Specifications of AD9772A
Available stocks
Related parts for AD9772A
AD9772A Summary of contents
Page 1
... The AD9772A can be driven by the on-chip reference variety of external reference voltages. The full-scale current of the AD9772A can be adjusted over range, thus providing additional gain-ranging capabilities. The AD9772A is available in a 48-lead LQFP package and is specified for operation over the industrial temperature range of – ...
Page 2
... Single-Ended, Unbuffered Voltage Output............................. 26 Single-Ended, Buffered Voltage Output.................................. 27 Power and Grounding Considerations.................................... 27 Applications Information .............................................................. 29 Multicarrier ................................................................................. 29 Baseband Single-Carrier Applications .................................... 30 Direct IF....................................................................................... 30 AD9772A Evaluation Board ......................................................... 32 Schematics................................................................................... 33 Evaluation Board Layout........................................................... 35 Outline Dimensions ....................................................................... 38 Ordering Guide .......................................................................... 38 Change to Digital Filter Specifications ...........................................5 Ordering Guide Updated .................................................................6 Change to Pin Function Descriptions ............................................7 Change to Figure 13a and Figure 13b ...
Page 3
... MSPS on-chip PLL clock multiplier generates all of the internal high speed clocks required by the interpolation filter and DAC. 6. The current output(s) of the AD9772A can easily be configured for various single-ended or differential circuit topologies. Rev Page AD9772A ...
Page 4
... AD9772A SPECIFICATIONS DC SPECIFICATIONS AVDD = 3.3 V, CLKVDD = 3.3 V, PLLVDD = 0 V, DVDD = 3 MIN MAX Table 1. Parameter RESOLUTION 1 DC ACCURACY Integral Linearity Error (INL) Differential Nonlinearity (DNL) Monotonicity (12-Bit) ANALOG OUTPUT Offset Error Gain Error Without Internal Reference With Internal Reference Full-Scale Output Current ...
Page 5
... MHz with DIV1 and DIV0 = 0 V. DATA OUT 5 Measured with PLL enabled MSPS and f DATA 6 Measured over a 3 3.6 V range. Min Typ 3.1 3.3 6.0 253 −0.6 −0.025 − MHz. OUT Rev Page AD9772A Max Unit 3 272 mW +0 FSR/V +0.025 % of FSR/V +85 °C ...
Page 6
... AD9772A DYNAMIC SPECIFICATIONS AVDD = 3.3 V, CLKVDD = 3.3 V, DVDD = 3.3 V, PLLVDD = 3 MIN MAX output, 50 Ω doubly terminated, unless otherwise noted. Table 2. Parameter DYNAMIC PERFORMANCE Maximum DAC Output Update Rate (f Output Settling Time (t ) (to 0.025 Output Propagation Delay ( Output Rise Time (10% to 90%) ...
Page 7
... Typ Max 2 0.9 −10 +10 −10 + 0.75 1.5 2.25 0.5 1.5 1.5 2.1 1.3 1.6 1.5 −0.7 −0.4 3.3 3.7 1.5 1.9 2.8 1.8 3.3 3.0 0 LPW OUTA OR I OUTB 0.025% Figure 3. Timing Diagram—PLL Clock Multiplier Disabled AD9772A Unit V V μA μ 0.025% ...
Page 8
... AD9772A DIGITAL FILTER SPECIFICATIONS AVDD = 3.3 V, CLKVDD = 3.3 V, PLLVDD = 0 V, DVDD = 3 MIN MAX 50 Ω doubly terminated, unless otherwise noted. Table 4. Parameter MAXIMUM INPUT DATA RATE (f ) DATA DIGITAL FILTER CHARACTERISTICS 1 Pass-Bandwidth : 0.005 dB Pass-Bandwidth: 0.01 dB Pass-Bandwidth: 0.1 dB Pass-Bandwidth: −3 dB LINEAR PHASE (FIR IMPLEMENTATION) STOP BAND REJECTION ...
Page 9
... AVDD + 0.3 V −0 Table 7. Thermal Resistance DVDD + 0.3 V Package Type −0 CLKVDD + 0.3 V 48-Lead LQFP −0 CLKVDD + 0.3 V ESD CAUTION −0 PLLVDD + 0.3 V 125°C −65°C to +150°C 300°C Rev Page AD9772A θ θ Unit °C/W ...
Page 10
... PLL is locked to the input clock. The maximum fanout is 1 (that is, <10 pF). 26 RESET Internal Divider Reset. This pin can reset the internal driver to synchronize the internal 1× clock to the input data and/or multiple AD9772A devices. The reset is initiated if this pin is momentarily brought high when PLL is disabled. 27, 28 DIV1, DIV0 PLL Prescaler Divide Ratio ...
Page 11
... Full-Scale Current Output Adjust Complementary DAC Current Output. Full-scale current is selected when all data bits are 0s. OUTB DAC Current Output. Full-scale current is selected when all data bits are 1s. OUTA 45, 46 AVDD Analog Supply Voltage (3 3.5 V). Rev Page AD9772A ...
Page 12
... AD9772A TERMINOLOGY Linearity Error (Also Called Integral Nonlinearity or INL) Linearity error is defined as the maximum deviation of the actual analog output from the ideal output and is determined by a straight line drawn from zero to full scale. Differential Nonlinearity (DNL) DNL is the measure of the variation in analog value, normalized to full scale that is associated with a 1 LSB change in digital input code ...
Page 13
... CONTROL ZERO 2× FIR 14-BIT DAC STUFF INTERPOLATION MUX FILTER 1.2V REFERENCE AND CONTROL AMP ACOM AVDD REFLO 3.3V Figure 7. Basic AC Characterization Test Setup Rev Page AD9772A PLLCOM LPF PLLVDD TO FSEA30 SPECTRUM MINI-CIRCUITS ANALYZER I T1-1T OUTA 100Ω I OUTB 0.1µF REFIO 50Ω ...
Page 14
... AD9772A TYPICAL PERFORMANCE CHARACTERISTICS AVDD = 3.3 V, CLKDD = 3.3 V, PLLVDD = 0 V, DVDD = 3 IN-BAND OUT-OF-BAND 0 –20 –40 –60 –80 –100 (MHz) OUT Figure 8. Single-Tone Spectral Characteristics @ f DATA 90 0dBFS 85 –6dBFS –12dBFS (MHz) OUT Figure 9. In-Band SFDR vs. f ...
Page 15
... Figure 18. Third-Order IMD Products vs 160 MSPS Figure 19. Third-Order IMD Products vs. f Rev Page AD9772A –6dBFS –3dBFS 0dBFS (MHz) OUT @ MSPS OUT DATA –6dBFS –3dBFS 0dBFS ...
Page 16
... AD9772A 160MSPS DATA f = 65MSPS DATA DATA –20 –15 –10 A (dBFS) OUT Figure 20. Third-Order IMD Products vs 160MSPS 70 DATA –20 –15 –10 A (dBFS) OUT Figure 21. Third-Order IMD Products vs –3dBFS 80 75 0dBFS ...
Page 17
... For applications requiring the synthesis of IF signals, users should consider operating the AD9772A in a direct IF mode. In this case, the zero-stuffing option should be considered when synthesizing and selecting IFs beyond the input data rate the reconstructed IF falls below f may or may not be beneficial ...
Page 18
... AD9772A In many band-limited applications, the images from the reconstruction process must be suppressed by an analog filter following the DAC. The complexity of this analog filter is typically determined by the proximity of the desired fundamental to the first image and the required amount of image suppression. Adding to the complexity of this analog filter is the requirement of compensating for the sin(x)/x response of the DAC ...
Page 19
... FREQUENCY ( DATA BASEBAND REGION Figure 29. Effects of Zero-Stuffing on the Sin(x)/x Response of the DAC For instance, if the digital data into the AD9772A represents a baseband signal centered around f /4 with a pass band of DATA f /10, the reconstructed baseband signal output from the DATA AD9772A experiences only a 0.18 dB amplitude variation over its pass band, with the first image occurring at 7/4 × ...
Page 20
... AD9772A remain DATA unaffected with or without the PLL clock multiplier enabled. The effects of phase noise on the AD9772A SNR performance become more noticeable at higher reconstructed output fre- quencies and signal levels. Figure 31 compares the phase noise of a full-scale sine wave at exactly f (and therefore carrier frequencies) with the optimum DIV1 and DIV0 settings ...
Page 21
... MOD1 and MOD0 active high). The clock distribution circuitry remains enabled, providing a 1× internal clock at PLLLOCK. Digital input data is latched into the AD9772A on every other rising edge of the differential clock input. The rising edge that corresponds to the input latch immediately precedes the rising edge of the 1× ...
Page 22
... R as shown in Equation 8. OUTA REFERENCE OPERATION , OUTFS The AD9772A contains an internal 1.20 V band gap reference that can easily be disabled and overridden by an external is a function of both reference. REFIO serves as either an output or input, depend- B ing on whether the internal or external reference is selected. If ...
Page 23
... I OUTFS 62.5 μA and 625 μA. The wide adjustment span of I vides several application benefits. The first benefit relates directly to the power dissipation of the AD9772A DAC, which is proportional to I (see the Power Dissipation section). OUTFS The second benefit relates to the 20 dB adjustment, which is useful for system gain control purposes ...
Page 24
... AD9772A of the output stage and affect the reliability of the AD9772A. The positive output compliance range is slightly dependent on the full-scale output current Operation beyond the OUTFS positive compliance range induces clipping of the output signal, which severely degrades the AD9772A linearity and distortion performance ...
Page 25
... V to 3.5 V. This mode can be activated by applying a Logic Level 1 to the SLEEP pin. The AD9772A takes less than power down and then approximately 15 μs to power up. ...
Page 26
... The differential circuit shown in Figure 49 provides the necessary level shifting required in a single-supply system. In this case, AVDD, the positive analog supply for both the AD9772A and the op amp, is also used to level-shift the differential output of the AD9772A to midsupply (that is, AVDD/2). The AD8057 is a suitable op amp for this application. ...
Page 27
... OUTFS FB SUPPLY Maintaining low noise on power supplies and ground is critical for achieving optimum results from the AD9772A. If properly implemented, ground planes can perform a host of functions on high speed circuit boards, such as bypassing and shielding current transport. In mixed-signal designs, the analog and digital portions of the board should be distinct from each other, ...
Page 28
... AD9772A optimum performance. Care should be taken to ensure that the ground plane is uninterrupted over crucial signal paths. On the digital side, this includes the digital input lines running to the DAC. On the analog side, this includes the DAC output signal, the reference signal, and the supply feeders. ...
Page 29
... MHz band. In this example, the AD9772A exhibits an SFDR performance of 74 dBc and a carrier-to-noise ratio (CNR dB. Figure 55 shows a spectral plot of the AD9772A operating at 52 MSPS, reconstructing four equal GSM-modulated carriers spread over a 15 MHz band. The SFDR and CNR (in 100 kHz BW) are measured dBc and 83.4 dB, respectively, and have a channel power of − ...
Page 30
... ACPR performance is theoretically 83 dB and the peak-to-rms ratio is 12.4 dB. As Figure 56 reveals, the AD9772A is capable of approximately 78 dB ACPR performance when one accounts for the additive noise/distortion contributed by the Rohde & Schwarz FSEA30 spectrum analyzer. – ...
Page 31
... IF filter while the AD9772A is reconstructing a waveform. Figure 59 shows an example in which four carriers are tuned around 18 MHz with a digital upconverter operating at 52 MSPS such that when reconstructed by the AD9772A in the IF mode, these carriers fall around a 70 MHz IF. –10 –20 – ...
Page 32
... A voltage of approximately 1.2 V will appear at the TP6 (REFIO) test point. To disable the internal reference, configure JP4 in the external position and drive TP6 with an external voltage reference. Lastly, the AD9772A can be placed in the sleep mode by driving the TP11 test point with a logic level high input signal. Rev Page ...
Page 33
... IN4 4 4 IN3 5 5 IN2 6 6 IN1 7 7 LSB IN0 8 8 INCLOCK 9 9 INRESET 10 10 RED +V S TP20 C18 0.1µF AD8055 AMPOUT 6 1 OUT J13 2 BLK –V S TP19 C17 0.1µF TP22 DVDD TP23 TP24 AVDD TP25 TP26 CLKVDD TP27 AD9772A ...
Page 34
... TP11 SLEEP 36 PIN 1 35 LPF IDENTIFIER CLK– 30 AD9772A CLK+ 29 DIV0 28 DIV1 27 26 PLLLOCK C11 TP3 0.1µF WHT TP28 WHT TP4 C12 WHT 1µ ...
Page 35
... EVALUATION BOARD LAYOUT Figure 62. Silkscreen Layer—Top Figure 63. Component-Side PCB Layout (Layer 1) Rev Page AD9772A ...
Page 36
... AD9772A Figure 64. Ground Plane PCB Layout (Layer 2) Figure 65. Power Plane PCB Layout (Layer 3) Rev Page ...
Page 37
... Figure 66. Solder-Side PCB Layout (Layer 4) Figure 67. Silkscreen Layer—Bottom Rev Page AD9772A ...
Page 38
... SEATING 0.05 PLANE VIEW A ROTATED 90° CCW ORDERING GUIDE Model Temperature Range AD9772AAST −40°C to +85°C 1 AD9772AASTZ −40°C to +85°C AD9772AASTRL −40°C to +85°C 1 AD9772AASTZRL −40°C to +85°C AD9772A- RoHS Compliant Part. 9.20 9.00 SQ 0.75 1.60 8.80 0.60 MAX 0. PIN 1 TOP VIEW ...
Page 39
... NOTES Rev Page AD9772A ...
Page 40
... AD9772A NOTES ©2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D02253-0-2/08(C) Rev Page ...