AD9772A Analog Devices, AD9772A Datasheet - Page 7

• Manufacturer Part Number: AD9772A
• Manufacturer: Analog Devices

Specifications of AD9772A

• Resolution (bits): 14bit
• Dac Update Rate: 160MSPS
• Dac Settling Time: 11ns
• Max Pos Supply (v): +3.6V
• Single-supply: Yes
• Dac Type: Current Out
• Dac Input Format: Par

DIGITAL SPECIFICATIONS
T
Table 3.
Parameter
DIGITAL INPUTS
CLOCK INPUTS
PLL CLOCK ENABLED (SEE Figure 2)
PLL CLOCK DISABLED (SEE Figure 3)
1
DB0 TO DB13
CLK+ – CLK–
MOD0, MOD1, DIV0, DIV1, SLEEP, RESET have typical input currents of 15 μA.
MIN
Logic 1 Voltage
Logic 0 Voltage
Logic 1 Current
Logic 0 Current
Input Capacitance
Input Voltage Range
Common-Mode Voltage
Differential Voltage
Input Setup Time (t
Input Hold Time (t
Latch Pulse Width (t
Input Setup Time (t
Input Hold Time (t
Latch Pulse Width (t
CLK+/CLK− to PLLLOCK Delay (t
PLLLOCK (V
PLLLOCK (V
to T
T
T
T
T
T
T
T
T
T
T
A
A
A
A
A
A
A
A
A
A
I
I
OUTA
OUTB
= 25°C
= −40 to +85°C
= 25°C
= −40 to +85°C
= 25°C
= −40 to +85°C
= 25°C
= −40 to +85°C
= 25°C
= −40 to +85°C
OR
Figure 2. Timing Diagram—PLL Clock Multiplier Enabled
MAX
, AVDD = 3.3 V, CLKVDD = 3.3 V, PLLVDD = 0 V, DVDD = 3.3 V, I
OH
OL
), T
), T
1
A
A
= 25°C
= 25°C
H
H
)
)
S
S
t
LPW
LPW
)
)
S
), T
), T
A
A
t
PD
= 25°C
= 25°C
t
LPW
t
H
OD
)
0.025%
t
ST
0.025%
Rev. C | Page 7 of 40
DB0 TO DB13
CLK+ – CLK–
PLLLOCK
I
I
OUTFS
OUTA
OUTB
Min
2.1
−10
−10
0
0.75
0.5
1.5
2.1
1.3
1.6
1.5
−0.7
−0.4
3.3
3.7
1.5
1.9
1.8
3.0
Figure 3. Timing Diagram—PLL Clock Multiplier Disabled
OR
= 20 mA, unless otherwise noted.
t
S
Typ
3
0
5
1.5
1.5
t
OD
t
PD
t
t
LPW
H
Max
0.9
+10
+10
3
2.25
2.8
3.3
0.3
0.025%
t
ST
AD9772A
Unit
V
V
μA
μA
pF
V
V
V
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
V
V
0.025%