AD9772A Analog Devices, AD9772A Datasheet - Page 24

• Manufacturer Part Number: AD9772A
• Manufacturer: Analog Devices

Specifications of AD9772A

• Resolution (bits): 14bit
• Dac Update Rate: 160MSPS
• Dac Settling Time: 11ns
• Max Pos Supply (v): +3.6V
• Single-supply: Yes
• Dac Type: Current Out
• Dac Input Format: Par

AD9772A
of the output stage and affect the reliability of the AD9772A.
The positive output compliance range is slightly dependent on
the full-scale output current, I
positive compliance range induces clipping of the output signal,
which severely degrades the AD9772A linearity and distortion
performance.
Operating the AD9772A with reduced voltage output swings
at I
configuration reduces the signal dependency of its output
impedance, thus enhancing distortion performance. Although
the voltage compliance range of I
−1.0 V to +1.25 V, optimum distortion performance is achieved
when the maximum full-scale signal at I
exceed approximately 0.5 V. Using a properly selected
transformer with a grounded center tap allows the AD9772A to
provide the required power and voltage levels to different loads
while maintaining reduced voltage swings at I
DC-coupled applications requiring a differential or single-
ended output configuration should size R
to the Output Configurations section for examples of various
output configurations.
The most significant improvement in the AD9772A distortion
and noise performance is realized using a differential output
configuration. The common-mode error sources of both I
and I
rejection of a transformer or differential amplifier. These
common-mode error sources include even-order distortion
products and noise. The enhancement in distortion performance
becomes more significant as the reconstructed waveform’s
frequency content increases and/or its amplitude decreases. The
distortion and noise performance of the AD9772A is also
dependent on the full-scale current setting, I
can be set between 2 mA and 20 mA, selecting an I
provides the best distortion and noise performance.
In summary, the AD9772A achieves the optimum distortion
and noise performance under the following conditions:
•
•
•
•
Note that the majority of the ac characterization curves for the
AD9772A are performed with these operating conditions.
DIGITAL INPUTS/OUTPUTS
The AD9772A consists of several digital input pins used for
data, clock, and control purposes. It also contains a single
digital output pin, PLLLOCK, which is used to monitor the
status of the internal PLL clock multiplier or provide a 1× clock
output. The 14-bit parallel data inputs follow standard positive
binary coding, where DB13 is the most significant bit (MSB)
and DB0 is the least significant bit (LSB). I
scale output current when all data bits are at Logic 1. I
OUTA
Positive voltage swing at I
Differential operation
I
PLL clock multiplier disabled
OUTB
OUTFS
and I
B
can be substantially reduced by the common-mode
set to 20 mA
OUTB
in a differential or single-ended output
OUTFS
OUTA
OUTA
. Operation beyond the
and I
and I
OUTA
OUTB
LOAD
OUTFS
OUTA
OUTB
B
limited to 0.5 V
and I
OUTA
accordingly. Refer
. Although I
B
produces a full-
extends from
OUTFS
OUTB
and I
of 20 mA
B
OUTB
does not
OUTB
OUTA
OUTFS
B
.
Rev. C | Page 24 of 40
produces a complementary output with the full-scale current
split between the two outputs as a function of the input code.
The digital interface is implemented using an edge-triggered
master slave latch and is designed to support an input data rate as
high as 160 MSPS. The clock can be operated at any duty cycle that
meets the specified latch pulse width, as shown in Figure 2 and
Figure 3. The setup and hold times can also be varied within the
clock cycle as long as the specified minimum times are met. The
digital inputs (excluding CLK+ and CLK−) are CMOS compatible
with its logic thresholds, V
digital positive supply (that is, DVDD or CLKVDD) or
The internal digital circuitry of the AD9772A is capable of
operating over a digital supply range of 3.1 V to 3.5 V. As a
result, the digital inputs can also accommodate TTL levels when
DVDD is set to accommodate the maximum high level voltage
of the TTL drivers V
typically ensures proper compatibility with most TTL logic
families, series 200 Ω resistors are recommended between the
TTL logic driver and digital inputs to limit the peak current
through the ESD protection diodes if V
by more than 300 mV. Figure 42 shows the equivalent digital
input circuit for the data and control inputs.
The AD9772A features a flexible differential clock input operating
from separate supplies (that is, CLKVDD, CLKCOM) to achieve
optimum jitter performance. The two clock inputs, CLK+ and
CLK−, can be driven from a single-ended or differential clock
source. For single-ended operation, CLK+ should be driven by a
single-ended logic source, and CLK− should be set to the logic
source’s threshold voltage via a resistor divider/capacitor network
referenced to CLKVDD as shown in Figure 43. For differential
operation, both CLK+ and CLK− should be biased to CLKVDD/2
via a resistor divider network as shown in Figure 44. An RF
transformer as shown in Figure 7 can also be used to convert a
single-ended clock input to a differential clock input.
V
THRESHOLD
= DVDD/2 (±20%)
V
Figure 43. Single-Ended Clock Interface
THRESHOLD
Figure 42. Equivalent Digital Input
DIGITAL
INPUT
OH(MAX)
AD9772A
1kΩ
1kΩ
THRESHOLD
. Although a DVDD of 3.3 V
R
0.1µF
SERIES
, set to approximately half the
OH(MAX)
DVDD
CLK+
CLKVDD
CLK–
CLKCOM
exceeds DVDD