STA32813TR STMicroelectronics, STA32813TR Datasheet

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... Preset night-time listening mode – Preset TV AGC Table 1. Device summary Order code STA328 STA32813TR May 2008 2.1-channel high-efficiency digital audio system ® ! Input and output channel mapping ! AM noise-reduction and PWM frequency-shifting modes ...

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Contents Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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STA328 6.6 Configuration register F (addr 0x05 6.7 Volume control . ...

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Contents 7.6.7 7.6.8 7.6.9 7.6.10 7.6.11 7.6.12 7.6.13 7.6.14 7.6.15 7.6.16 7.6.17 7.7 Reading a coefficient from RAM . . . . . . . . . . . . . . . . . . . . . . ...

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STA328 1 Description 1.1 Overview The STA328 comprises digital audio processing, digital amplifier control and DDX output stage to create a high-power single-chip DDX high-efficiency, all digital amplification. The STA328 power section consists of four independent half-bridges. These can be ...

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Description 1.2 EQ processing Two channels of input data (re-sampled if necessary kHz are provided to the EQ processing block. In this block four user-defined biquads can be applied to each of the two channels. Pre-scaling, ...

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STA328 1.4 Applications Figure 5. Application circuit for 2.1/2.0 configurable solution Description 7/57 ...

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Pin out 2 Pin out 2.1 Package pins Figure 6. Pin connections 2.2 Pin list Table 2. Pin list Number 1 I I/O 5 N.C. 6 I/O 7 I ...

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STA328 Table 2. Pin list Number 15 I I/O 18 I/O 19 I I I/O ...

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Pin out 2 signals (pins 23 and 24 The SDA (I C Data) and SCL (I (Chapter 5 on page 16 supported. GNDA and VDDA (pins 28 and 29) This is the 3.3 V analog supply for ...

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STA328 3 Electrical specifications Table 3. Absolute maximum ratings Symbol V 3.3 V I/O power supply (pins VDDA, VDD) DD33 V Voltage on input pins i V Voltage on output pins o T Storage temperature stg T Ambient operating temperature ...

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Electrical specifications 3.2 DC electrical specifications (3.3 V buffers) Operating conditions V Table 7. DC electrical specifications Symbol V Low level input voltage IL V High level input voltage IH V Schmitt trigger hysteresis hyst V Low level output ol ...

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STA328 Table 8. Power electrical characteristics (continued) Symbol Supply current from V operation I VCC (both channel switching) Overcurrent protection I threshold (short circuit current out-sh limit) Undervoltage protection V UV threshold t Output minimum pulse width pw-min Output power ...

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Electrical characteristics curves 4 Electrical characteristics curves Figure 9. Channel separation vs frequency dBr A dBr A Figure 10. THD vs output power - single ended THD (%) THD (%) 14/57 +10 + -10 -10 -20 -20 -30 ...

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STA328 Figure 11. THD vs output power - BTL THD (%) THD (%) Figure 12. THD vs frequency - BTL THD (%) THD (%) Vcc = 36 V Vcc = ...

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I C bus specification bus specification The STA328 supports the the I C bus as a transmitter and any device that reads the data as a receiver. The device that controls the ...

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STA328 5.3 Write operation Following the START condition the master sends a device select code with the RW bit set to 0. The STA328 acknowledges this and then the master writes the internal address byte. After receiving the internal byte ...

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I C bus specification Current address multi-byte read The multi-byte read modes can start from any internal address. Sequential data bytes will be read from sequential addresses within the STA328. The master acknowledges each data byte read and then ...

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STA328 6 Register description You must not reprogram the register bits marked “Reserved” important that these bits keep their default reset values. Table 9. Register summary Address Name D7 0x00 ConfA FDRB 0x01 ConfB C2IM 0x02 ConfC Reserved ...

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Register description Table 9. Register summary Address Name D7 0x1E A1cf2 C3B15 0x1F A1cf3 C3B7 0x20 A2cf1 C4B23 0x21 A2cf2 C4B15 0x22 A2cf3 C4B7 0x23 B0cf1 C5B23 0x24 B0cf2 C5B15 0x25 B0cf3 C5B7 0x26 Cfud Reserved Reserved Reserved Reserved RA ...

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STA328 bits determine the PLL factor generating the internal clock and the IR bit determines the oversampling ratio used internally. Table 11. IR and MCS settings for input sample rate and clock rate Input sample rate fs (kHz) 32, 44.1, ...

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Register description Table 15. Thermal warning adjustment bypass Bit R/W RST The on-chip STA328 power output block provides feedback to the digital controller using inputs to the power control block. The TWARN input is used to indicate ...

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STA328 6.2 Configuration register B (addr 0x01 C2IM C1IM 1 0 This register configures the serial data interface Table 17. Serial audio input interface format Bit R/W RST 3:0 RW 0000 The STA328 serial audio ...

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Register description Table 18. Supported serial audio input formats BICKI SAI [3: 1100 1110 0100 0100 1000 0100 1100 0001 0101 1001 1101 0010 0110 1010 1110 0000 0100 1000 0000 ...

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STA328 Table 19. Serial input data timing characteristics ( 192 kHz) BICKI frequency (slave mode) BICKI pulse width low (T0) (slave mode) BICKI pulse width high (T1) (slave mode) BICKI active to LRCKI edge delay (T2) BICKI ...

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Register description 6.3 Configuration register C (addr 0x02) D7 Reserved CSZ4 0 ® 6.3.1 DDX power output mode Table 22. DDX Bit R/W RST 1 ® The DDX power output mode selects how the DDX power devices can ...

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STA328 6.4 Configuration register D (addr 0x03 MME ZDE 0 1 Table 25. High-pass filter bypass Bit R/W RST The STA328 features an internal digital high-pass filter for the purpose of DC Blocking. The purpose ...

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Register description Table 29. Biquad coefficient link Bit R/W RST For ease of use, all channels can use the biquad coefficients loaded into the channel 1 coefficient RAM space by setting the BQL bit to 1. Therefore, ...

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STA328 6.5 Configuration register E (addr 0x04 SVE ZCE 1 1 Table 33. Max power correction variable Bit R/W RST enabling MPC and setting MPCV = 1, the max power correction becomes variable. By ...

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Register description Table 38. Zero-crossing volume enable Bit R/W RST The ZCE bit enables zero-crossing volume adjustments. When volume is adjusted on digital zero-crossings no clicks will be audible. Table 39. Soft volume update enable Bit R/W ...

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STA328 6.6 Configuration register F (addr 0x05 EAPD PWDN 0 Table 40. Output configuration selection Bit R/W RST 1 Table 41. Output configuration selection OCFG[1: Table 42. Invalid input detect mute enable ...

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Register description Table 44. Auto-EAPD on clock loss enable Bit R/W RST When ECLE is active, it issues a power device power down signal (EAPD) on clock loss detection. Table 45. Software power down Bit R/W RST ...

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STA328 6.7 Volume control 6.7.1 Master controls Master mute register (addr 0x06 Reserved Reserved 0 0 Master volume register (addr 0x07 MV7 MV6 1 1 Note: Value of volume derived from MVOL is dependent on AMV ...

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Register description mute” can be obtained by programming the value 0xFF to any channel volume register or the master volume register. When volume offsets are provided via the master volume register any channel whose total volume is less than -100 ...

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STA328 6.8 AutoMode registers 6.8.1 AutoModes EQ, volume, GC (addr 0x0B AMPS Reserved 1 0 Table 49. AutoMode EQ AMEQ[1, setting AMEQ to any setting other than 00 enables AutoMode EQ where biquads ...

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Register description 6.8.2 AutoMode AM/pre-scale/bass management scale (addr 0x0C XO3 XO2 0 0 Table 53. AutoMode AM switching enable Bit R/W RST 3:1 RW 000 n Table 54. AutoMode AM switching frequency selection AMAM[2:0] 000 ...

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STA328 Table 56. Crossover frequency selection (continued) XO[2:0] 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 6.8.3 Preset EQ settings (addr 0x0D Reserved Reserved 0 0 Table 57. Preset EQ selection PEQ[3:0] 00000 00001 00010 ...

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Register description Table 57. Preset EQ selection (continued) PEQ[3:0] 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111 6.9 Channel configuration registers 6.9.1 Channel 1 configuration (addr 0x0E) D7 C1OM1 C1OM0 0 6.9.2 Channel ...

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STA328 CxEQBP: " 0 perform EQ on channel X - normal operation " 1 bypass EQ on channel X Tone control (bass/treble) can be bypassed on a per channel basis. If tone control is bypassed on a given channel the ...

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Register description 6.10 Tone control (addr 0x11 TTC3 TTC2 0 1 Table 60. Tone control boost/cut selection BTC[3:0]/TTC[3:0] 0000 0001 … 0111 0110 0111 1000 1001 … 1101 1110 1111 40/ TTC1 TTC0 BTC3 1 ...

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STA328 6.11 Dynamics control 6.11.1 Limiter 1 attack/release threshold (addr 0x12 L1A3 L1A2 0 1 6.11.2 Limiter 1 attack/release threshold (addr 0x13 L1AT3 L1AT2 0 1 6.11.3 Limiter 2 attack/release rate (addr 0x14 L2A3 ...

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Register description and therefore the release will only occur if the limiter has already reduced the gain. The release threshold value can be used to set what is effectively a minimum dynamic range. This is helpful as over-limiting can reduce ...

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STA328 6.11.6 Anti-clipping mode Table 62. Limiter attack/release threshold selection (AC mode) LxAT[3:0] 0000 -12 0001 -10 0010 -8 0011 -6 0100 -4 0101 -2 0110 0 0111 +2 1000 +3 1001 +4 1010 +5 1011 +6 1100 +7 1101 ...

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Register description 6.11.7 Dynamic range compression mode Table 63. Limiter attack/release threshold selection (DRC mode) LxAT[3:0] 0000 -31 0001 -29 0010 -27 0011 -25 0100 -23 0101 -21 0110 -19 0111 -17 1000 -16 1001 -15 1010 -14 1011 -13 ...

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STA328 7 User programmable processing 7 biquad equation The biquads use the equation that follows. This is diagrammed in Y[n] = 2(b0/2)X[n] + 2(b1/2)X b2X 2(a1/2)Y a2Y ...

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User programmable processing 7.4 Mix/bass management The STA328 provides a post-EQ mixing block per channel. Each channel has 2 mixing coefficients, which are each 24-bit signed fractional multipliers, that correspond to the 2 channels of input to the mixing block. ...

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STA328 7.5 Calculating 24-bit signed fractional numbers from a dB value The pre-scale, mixing, and post-scale functions of the STA328 use 24-bit signed fractional multipliers to attenuate signals. These attenuations can also invert the phase and therefore range in value ...

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User programmable processing 7.6.6 Coefficient b2 data register bits 15:8 (addr 0x1B C2B15 C2B14 0 7.6.7 Coefficient b2 data register bits 7:0 (addr 0x1C C2B7 C2B6 0 7.6.8 Coefficient a1 data register bits 23:16 (addr 0x1D) ...

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STA328 7.6.14 Coefficient b0 data register bits 23:16 (addr 0x23 C5B23 C5B22 0 0 7.6.15 Coefficient b0 data register bits 15:8 (addr 0x24 C5B15 C5B14 0 7.6.16 Coefficient b0 data register bits 7:0 (addr 0x25) D7 ...

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User programmable processing 7.7 Reading a coefficient from RAM " write 8 bits of address to I " write 1 to bit R1 (D2 " read top 8 bits of coefficient in I " read middle 8 bits ...

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STA328 7.10 Writing a set of coefficients to RAM " write 8 bits of starting address to I " write top 8 bits of coefficient " write middle 8 bits of coefficient " write ...

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User programmable processing Table 64. RAM block for biquads, mixing, and scaling (continued) Index (decimal 52/57 ...

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STA328 7.11 Variable max power correction (addr 0x27, 0x28 MPCC15 MPCC14 0 MPCC7 MPCC6 1 MPCC bits determine the 16 MSBs of the MPC compensation coefficient. This coefficient is used in place of the default coefficient when MPCV ...

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Package mechanical data 8 Package mechanical data Figure 20. PowerSO-36 slug up outline drawing 54/57 STA328 ...

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STA328 Table 65. PowerSO-36 slug up dimensions Symbol Min A 3.25 A2 3. 0.03 b 0.22 c 0.23 D 15. 13.90 E1 10. 5.80 E4 2.90 e ...

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Revision history 9 Revision history Table 66. Document revision history Date Sep-2004 Jul-2005 May-2006 13-May-2008 56/57 Revision 1 Initial release 2 Added pins 7 and 25 in block diagram 3 Changed from product preview to maturity Updated device pin 1 ...

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