STA32813TR STMicroelectronics, STA32813TR Datasheet - Page 41

• Manufacturer Part Number: STA32813TR
• Description: IC DAS 2.1CH HI EFF POWERSO36
• Manufacturer: STMicroelectronics
• Series: DDX™r
• Type: Audio Ampr

Specifications of STA32813TR

• Mounting Type: Surface Mount
• Package / Case: 36-PowerSOIC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Applications: -
• Other names: 497-8876-2

STA328
6.11
6.11.1
6.11.2
6.11.3
6.11.4
6.11.5
Dynamics control
Limiter 1 attack/release threshold (addr 0x12)
Limiter 1 attack/release threshold (addr 0x13)
Limiter 2 attack/release rate (addr 0x14)
Limiter 2 attack/release threshold (addr 0x15)
Dynamics control description
The STA328 includes 2 independent limiter blocks. The purpose of the limiters is to
automatically reduce the dynamic range of a recording to prevent the outputs from clipping
in anti-clipping mode, or to actively reduce the dynamic range for a better listening
environment (such as a night-time listening mode, which is often needed for DVDs.) The two
modes are selected via the DRC bit in configuration register D (bit 5, address 0x03). Each
channel can be mapped to Limiter1, Limiter2, or not mapped.
If a channel is not mapped, that channel will clip normally when 0 dBFS is exceeded. Each
limiter will look at the present value of each channel that is mapped to it, select the
maximum absolute value of all these channels, perform the limiting algorithm on that value,
and then if needed adjust the gain of the mapped channels in unison.
The limiter attack thresholds are determined by the LxAT registers. When the attack
threshold has been exceeded, the limiter, when active, will automatically start reducing the
gain. The rate at which the gain is reduced when the attack threshold is exceeded is
dependent upon the attack rate register setting for that limiter. The gain reduction occurs on
a peak-detect algorithm.
The release of limiter, when the gain is again increased, is dependent on a RMS-detect
algorithm. The output of the volume/limiter block is passed through an RMS filter. The output
of this filter is compared to the release threshold, determined by the Release Threshold
register.
When the RMS filter output falls below the release threshold, the gain is increased at a rate
dependent upon the release rate register. The gain can never be increased past its set value
L1AT3
L2AT3
L1A3
L2A3
D7
D7
D7
D7
0
0
0
0
L1AT2
L2AT2
L1A2
L2A2
D6
D6
D6
D6
1
1
1
1
L1AT1
L2AT1
L1A1
L2A1
D5
D5
D5
D5
1
1
1
1
L1AT0
L2AT0
L1A0
L2A0
D4
D4
D4
D4
0
0
0
0
L1RT3
L2RT3
L1R3
L2R3
D3
D3
D3
D3
1
1
1
1
L1RT2
L2RT2
L1R2
L2R2
D2
D2
D2
D2
0
0
0
0
Register description
L1RT1
L2RT1
L1R1
L2R1
D1
D1
D1
D1
0
0
1
1
L1RT0
L2RT0
L1R0
L2R0
D0
D0
D0
D0
0
1
0
1
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