STA32813TR STMicroelectronics, STA32813TR Datasheet - Page 25

IC DAS 2.1CH HI EFF POWERSO36

STA32813TR

Manufacturer Part Number
STA32813TR
Description
IC DAS 2.1CH HI EFF POWERSO36
Manufacturer
STMicroelectronics
Series
DDX™r
Type
Audio Ampr
Datasheet

Specifications of STA32813TR

Mounting Type
Surface Mount
Package / Case
36-PowerSOIC
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Applications
-
Other names
497-8876-2
STA328
Table 19.
Figure 16. Serial input data timing
Table 20.
Table 21.
Each channel received via I
channel input mapping registers. This allows for flexibility in processing. The default settings
of these registers map each I
BICKI frequency (slave mode)
BICKI pulse width low (T0) (slave mode)
BICKI pulse width high (T1) (slave mode)
BICKI active to LRCKI edge delay (T2)
BICKI active to LRCKI edge delay (T3)
SDI valid to BICKI active setup (T4)
BICKI active to SDI hold time (T5)
5
6
7
Bit
Bit
RW
RW
RW
R/W
R/W
Serial input data timing characteristics (fs = 32 to 192 kHz)
Delay serial clock enable
Channel input mapping
0
0
1
LRCKI
BICKI
RST
RST
Parameter in
SDI
C1IM
C2IM
DSCKE
T2
2
Name
Name
S can be mapped to any internal processing channel via the
2
S input channel to its corresponding processing channel.
Figure 16
T4
T3
0: processing channel 1 receives left I
1: processing channel 1 receives right I
0: processing channel 2 receives left I
1: processing channel 2 receives right I
Delay serial clock enable:
0: no serial clock delay
1: serial clock delay by 1 core clock cycle to tolerate
anomalies in some I
T5
T0
T1
12.5 MHz max.
40 ns min.
40 ns min.
20 ns min.
20 ns min.
20 ns min.
20 ns min.
2
S master devices
Description
Description
Register description
Value
2
2
S input
S input
2
2
S input
S input
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