ADM1064 Analog Devices, ADM1064 Datasheet
ADM1064
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ADM1064 Summary of contents
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... The ADM1064 Super Sequencer® configurable supervisory/ sequencing device that offers a single-chip solution for supply monitoring and sequencing in multiple supply systems. In addition to these functions, the ADM1064 integrates a 12-bit ADC that can be used to accurately read back separate voltages. The device also provides programmable inputs for moni- toring undervoltage faults, overvoltage faults, or out-of-window faults supplies ...
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... Changes to Inputs Section............................................................. 14 Changes to Outputs Section.......................................................... 17 Added Default Output Configuration Section ........................... 18 Changes to Fault Reporting Section ............................................ 22 Changes to Voltage Readback Section......................................... 23 Changes to Identifying the ADM1064 on the SMBus Section. 27 Changes to Figure 31 and Figure 32............................................. 28 Changes to Figure 43 Caption ...................................................... 32 Change to Ordering Guide............................................................ 32 1/05—Rev Rev A Changes to Figure 1...........................................................................1 Changes to Absolute Maximum Ratings Section ...
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... VCCP Figure 2. Detailed Block Diagram Rev Page SDA SCL A1 A0 SMBus INTERFACE OSC DEVICE CONTROLLER EEPROM CONFIGURABLE OUTPUT DRIVER PDO1 (HV) PDO2 PDO3 PDO4 PDO5 CONFIGURABLE OUTPUT DRIVER PDO6 (HV) CONFIGURABLE OUTPUT DRIVER PDO7 (LV) PDO8 PDO9 CONFIGURABLE OUTPUT DRIVER PDO10 (LV) PDOGND ADM1064 ...
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... ADM1064 SPECIFICATIONS 3 14 VPx = 3 6.0 V Table 1. Parameter POWER SUPPLY ARBITRATION VH, VPx VPx VH VDDCAP C VDDCAP POWER SUPPLY Supply Current VPx Additional Currents All PDO FET Drivers On Current Available from VDDCAP ADC Supply Current EEPROM Erase Current SUPPLY FAULT DETECTORS VH Pin ...
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... V 0 400 kHz 1.3 μs 0.6 μs 0.6 μs 0.6 μs 1.3 μs 0.6 μs 300 ns 300 ns Rev Page ADM1064 = 2.048 V REFIN = 0 μ μA OH < (pull-up to VDDCAP or VPx VPx = 6 ≤ 14.4 V PDO = 5 5 ...
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... ADM1064 Parameter Data Setup Time, t SU;DAT Data Hold Time, t HD;DAT Input Low Current SEQUENCING ENGINE TIMING State Change Time 1 At least one of the VH, VPx pins must be ≥3 maintain the device supply on VDDCAP. 2 Specification is not production tested but is supported by characterization data at initial product release. ...
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... INDICATOR VX2 3 VX3 4 VX4 5 ADM1064 VX5 6 TOP VIEW VP1 7 (Not to Scale) VP2 8 VP3 9 VP4 CONNECT Figure 4. TQFP Pin Configuration ADM1064 NC 36 PDO1 35 PDO2 34 PDO3 33 PDO4 32 PDO5 31 PDO6 30 PDO7 29 PDO8 28 PDO9 27 PDO10 ...
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... ADM1064 Pin No. 1 Mnemonic LFCSP TQFP 38 45 AUX1 39 46 VDDCAP GND 1 Note that the LFCSP has an exposed pad on the bottom. This pad connect (NC). If possible, this pad should be soldered to the board for improved mechanical stability typical application, all ground pins are connected together. ...
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... −0 +0.3 V Table 4. Thermal Resistance ±5 mA Package Type ±20 mA 40-Lead LFCSP 150°C 48-Lead TQFP −65°C to +150°C 215°C ESD CAUTION 2000 V Rev Page ADM1064 θ Unit JA 25 °C/W 50 °C/W ...
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... ADM1064 TYPICAL PERFORMANCE CHARACTERISTICS (V) VP1 Figure 5. V vs. V VDDCAP (V) VH Figure 6. V vs. V VDDCAP 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0 (V) VP1 Figure 7. I vs. V (VP1 as Supply) VP1 VP1 VP1 ...
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... LOAD 12000 10000 8000 6000 4000 2000 Figure 16. ADC Noise, Midcode Input, 10,000 Reads LOAD Rev Page ADM1064 1000 2000 3000 4000 CODE Figure 14. DNL for ADC 1000 2000 3000 4000 CODE Figure 15. INL for ADC 9894 25 81 ...
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... ADM1064 2.058 2.053 2.048 2.043 2.038 –40 – TEMPERATURE (°C) Figure 17. REFOUT vs. Temperature VP1 = 3.0V VP1 = 4.75V 60 80 100 Rev Page ...
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... A supply comparator chooses the highest input to provide the on-chip supply. There is minimal switching loss with this architecture (~0.2 V), resulting in the ability to power the ADM1064 from a supply as low as 3.0 V. Note that the supply on the VXx pins cannot be used to power the device. An external capacitor to GND is required to decouple the on-chip supply from noise ...
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... Table 6 shows the details of each input. PROGRAMMING THE SUPPLY FAULT DETECTORS The ADM1064 can have SFDs on its 10 input channels. These highly programmable reset generators enable the supervision supply voltages. The supplies can be as low as 0.573 V and as high as 14 ...
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... Thus, potentially any supply can be divided down into the input range of the VXx pin and supervised, enabling the ADM1064 to monitor other supplies, such as +24 V, +48 V, and − additional supply supervision function is available when the VXx pins are selected as digital inputs ...
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... Because of this, the PDOx pins are pulled to GND by a weak (20 kΩ) on-chip pull-down resistor. As the input supply to the ADM1064 ramps up on VPx or VH, all PDOx pins behave as follows: Input supply = 1.2 V. The PDOs are high impedance. ...
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... If VP2 is not okay State DIS3V3. PWRGD If VX1 is high State DIS2V5. MONITOR FAULT The ADM1064 offers state definitions. The signals monitored to indicate the status of the input pins are the outputs of the SFDs. WARNINGS The SE also monitors warnings. These warnings can be generated ...
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... ADM1064 SEQUENCING ENGINE APPLICATION EXAMPLE The application in this section demonstrates the operation of the SE. Figure 25 shows how the simple building block of a single SE state can be used to build a power-up sequence for a three- supply system. Table 8 lists the PDOs for each state in the same SE implementation ...
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... FAULT FAULT AND STATUS REPORTING The ADM1064 has a fault latch for recording faults. Two registers, FSTAT1 and FSTAT2, are set aside for this purpose. A single bit is assigned to each input of the device, and a fault on that input sets the relevant bit. The contents of the fault register can be read out over the SMBus to determine which input(s) faulted ...
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... READING or input into the SE to determine what sequencing action the ADC ADM1064 should take. Only one register is provided for each input channel. Therefore, either an undervoltage threshold or overvoltage threshold (but not both) can be set for a given channel. The round- robin circuit can be enabled via an SMBus write can be programmed to turn on in any state in the SE program ...
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... SYSTEM RESET VX5 PDO8 PDO9 PDO10 REFOUT REFIN VCCP VDDCAP GND 10µF 10µF 10µF 3.3V OUT DC-TO-DC4 EN Figure 29. Applications Diagram Rev Page 12V OUT 5V OUT 3V OUT IN DC-TO-DC1 EN OUT 3.3V OUT IN DC-TO-DC2 EN OUT 2.5V OUT IN DC-TO-DC3 EN OUT 1.8V OUT 3.3V OUT IN LDO EN OUT 0.9V OUT IN 1.2V OUT OUT ADM1064 ...
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... EEPROM contents to the RAM again, as described in Option 3, restoring the ADM1064 to its original configuration. The topology of the ADM1064 makes this type of operation possible ...
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... Therefore, access to the ADM1064 is restricted until the download is complete. Identifying the ADM1064 on the SMBus The ADM1064 has a 7-bit serial bus slave address (see Table 10). The device is powered up with a default serial bus address. The five MSBs of the address are set to 01001; the two LSBs are determined by the logical states of Pin A1 and Pin A0 ...
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... ADM1064 The device also has several identification registers (read-only) that can be read across the SMBus. Table 11 lists these registers with their values and functions. Table 11. Identification Register Values and Functions Name Address Value Function MANID 0xF4 0x41 Manufacturer ID for Analog Devices ...
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... SLAVE FRAME 2 DATA BYTE ACK. BY MASTER FRAME N DATA BYTE HD; STA SU; STA t SU; DAT S Figure 33. Serial Bus Timing Diagram Rev Page ADM1064 9 D0 ACK. BY MASTER STOP NO ACK. BY MASTER t SU; STO P ...
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... The slave asserts an ACK on SDA. 10. The master asserts a stop condition on SDA to end the transaction. In the ADM1064, the write byte/word protocol is used for three purposes: • To write a single byte of data to the RAM. In this case, the command byte is RAM Address 0x00 to RAM Address 0xDF, and the only data byte is the actual data, as shown in Figure 36 ...
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... The master asserts a NACK on SDA. 6. The master asserts a stop condition on SDA, and the transaction ends. In the ADM1064, the receive byte protocol is used to read a single byte of data from a RAM or EEPROM location whose address has previously been set by a send byte or write byte/word operation, as shown in Figure 40. ...
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... In a block read operation, the master device reads a block of data from a slave device. The start address for a block read must have been set previously. In the ADM1064, this is done by a send byte operation to set a RAM address write byte/word operation to set an EEPROM address. The block read operation itself consists ...
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... EXPOSED 4.10 SQ PAD 3.95 (BOT TOM VIEW 0.25 MIN 4.50 REF FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 9.00 BSC PIN 1 7.00 BSC SQ TOP VIEW (PINS DOWN 0.50 0.27 BSC 0.22 LEAD PITCH 0.17 Package Option CP-40-1 SU-48 ADM1064 ...
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... ADM1064 NOTES Rev Page ...
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... NOTES Rev Page ADM1064 ...
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... ADM1064 NOTES ©2004–2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04633-0-6/11(D) Rev Page ...