ADM1064 Analog Devices, ADM1064 Datasheet - Page 5

• Manufacturer Part Number: ADM1064
• Manufacturer: Analog Devices

Specifications of ADM1064

• # Supplies Monitored: 10
• Volt Monitoring Accuracy: 1%
• # Output Drivers: 10
• Fet Drive/enable Output: Both
• Voltage Readback: 12-bit ADC
• Package: 40 ld LFCSP ,48 ld TQFP

Parameter
REFERENCE OUTPUT
PROGRAMMABLE DRIVER OUTPUTS
DIGITAL INPUTS (VXx, A0, A1)
SERIAL BUS DIGITAL INPUTS (SDA, SCL)
SERIAL BUS TIMING
Offset Error
Input Noise
Reference Output Voltage
Load Regulation
Minimum Load Capacitance
PSRR
Input High Voltage, V
Input Low Voltage, V
Input High Current, I
Input Low Current, I
Input Capacitance
Input High Voltage, V
Input Low Voltage, V
Output Low Voltage, V
Clock Frequency, f
Bus Free Time, t
Start Setup Time, t
Stop Setup Time, t
Start Hold Time, t
SCL Low Time, t
SCL High Time, t
SCL, SDA Rise Time, t
SCL, SDA Fall Time, t
Conversion Time
High Voltage (Charge Pump) Mode
Standard (Digital Output) Mode
Three-State Output Leakage Current
Oscillator Frequency
Programmable Pull-Down Current, I
(PDO1 to PDO6)
Output Impedance
V
I
(PDO1 to PDO10)
V
V
I
I
R
I
OUTAVG
OL
SINK
SOURCE
OH
OH
OL
PULL-UP
2
2
(VPx)
2
BUF
LOW
HIGH
3
HD;STA
SCLK
SU;STA
SU;STO
IL
F
IL
IH
IL
R
IH
IH
OL
2
PULL-DOWN
Min
2.043
1
11
10.5
2.4
V
0
16
90
2.0
−1
2.0
1.3
0.6
0.6
0.6
1.3
0.6
PU
− 0.3
Typ
0.44
84
0.25
2.048
−0.25
0.25
60
500
12.5
12
20
20
100
5
20
Rev. D | Page 5 of 32
Max
±2
2.053
14
13.5
4.5
0.50
20
60
29
2
10
110
0.8
1
0.8
0.4
400
300
300
ms
kΩ
kHz
Unit
ms
LSB
LSB rms
V
mV
mV
μF
dB
kΩ
V
V
μA
V
V
V
V
mA
mA
mA
μA
V
V
μA
μA
pF
μA
V
V
V
kHz
μs
μs
μs
μs
μs
μs
ns
ns
Test Conditions/Comments
One conversion on one channel
All 12 channels selected, averaging enabled
V
Direct input (no attenuator)
No load
Sinking current
Capacitor required for decoupling, stability
DC
I
I
2 V < V
V
V
V
I
Maximum sink current per PDOx pin
Maximum total sink for all PDOx pins
Internal pull-up
Current load on any VPx pull-ups, that is, total source
current available through any number of PDOx pull-up
switches configured onto any one VPx pin
V
All on-chip time delays derived from this clock
Maximum V
Maximum V
V
V
VDDCAP = 4.75 V, T
required
I
Sourcing current
OH
OH
OL
OUT
REFIN
PU
PU
PU
PDO
IN
IN
= 20 mA
= 0 μA
= 1 μA
= 5.5 V
= 0
(pull-up to VDDCAP or VPx) = 2.7 V, I
to VPx = 6.0 V, I
≤ 2.7 V, I
= −3.0 mA
= 14.4 V
= 2.048 V
OH
< 7 V
OH
IN
IN
= 5.5 V
= 5.5 V
= 0.5 mA
OH
A
= 25°C, if known logic state is
= 0 mA
ADM1064
OH
= 0.5 mA