CS8420-DSZ Cirrus Logic Inc, CS8420-DSZ Datasheet - Page 40

• Manufacturer Part Number: CS8420-DSZ
• Description: IC CONV S/R DGTL AUDIO 28-SOIC
• Manufacturer: Cirrus Logic Inc
• Type: Sample Rate Converterr

Specifications of CS8420-DSZ

• Applications: Digital Audio
• Mounting Type: Surface Mount
• Package / Case: 28-SOIC
• Audio Control Type: Sample Rate Converter
• Control Interface: 3 Wire, Serial
• Supply Voltage Range: 4.75V To 5.25V
• Operating Temperature Range: -40°C To +85°C
• Audio Ic Case Style: SOIC
• No. Of Pins: 28
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 598-1729

40
10.8
TSLIP
OSLIP
SRE
OVRGL
OVRGR
DETC
EFTC
RERR
TSLIP
7
Interrupt 1 Register Status (07h) (Read Only)
OSLIP
For all bits in this register, a “1” means the associated interrupt condition has occurred at least
once since the register was last read. A”0” means the associated interrupt condition has NOT
occurred since the last reading of the register. Reading the register resets all bits to 0, unless
the interrupt mode is set to level and the interrupt source is still true. Status bits that are masked
off in the associated mask register will always be “0” in this register. This register defaults to 00.
clocks the AES3 transmitter, is asynchronous to the data source, this bit will go high every time
a data sample is dropped or repeated. Also, when TCBL is an input, and when the SRC is not
in use, this bit will go high on receipt of a new TCBL signal.
Serial audio output port data slip interrupt. When the serial audio output port is in Slave mode,
and OLRCK is asynchronous to the port data source, this bit will go high every time a data sam-
ple is dropped or repeated. Also, when the SRC is used, and the SRC output goes to the output
serial port configured in Slave mode, this bit will indicate if the ratio of OMCK frequency to OL-
RCK frequency does not match what is set in the CLK1 and CLK0 bits.
Sample rate range exceeded indicator. Occurs if Fsi/Fso or Fso/Fsi exceeds 3.
Over-range indicator for left (A) channel SRC output. Occurs on internal over-range for left
channel data. Note that the CS8420 automatically clips over-ranges to plus or minus full scale.
Over-range indicator for right (B) channel SRC output. Occurs on internal over-range for right
channel data. Note that the CS8420 automatically clips over-ranges to plus or minus full scale
in the C bit buffer management process.
E to F C-buffer transfer interrupt. The source for this bit is true during the E to F buffer transfer
in the C bit buffer management process.
A receiver error has occurred. The Receiver Error register may be read to determine the nature
of the error which caused the interrupt.
AES3 transmitter source data slip interrupt. In data flows with no SRC, and where OMCK, which
D to E C-buffer transfer interrupt. The source for this bit is true during the D to E buffer transfer
6
SRE
5
OVRGL
4
OVRGR
3
DETC
2
EFTC
1
CS8420
RERR
DS245F4
0