CS8420-DSZ Cirrus Logic Inc, CS8420-DSZ Datasheet - Page 74

• Manufacturer Part Number: CS8420-DSZ
• Description: IC CONV S/R DGTL AUDIO 28-SOIC
• Manufacturer: Cirrus Logic Inc
• Type: Sample Rate Converterr

Specifications of CS8420-DSZ

• Applications: Digital Audio
• Mounting Type: Surface Mount
• Package / Case: 28-SOIC
• Audio Control Type: Sample Rate Converter
• Control Interface: 3 Wire, Serial
• Supply Voltage Range: 4.75V To 5.25V
• Operating Temperature Range: -40°C To +85°C
• Audio Ic Case Style: SOIC
• No. Of Pins: 28
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 598-1729

74
13.7
Hardware Mode 6 Description
(AES3 Transmitter Only)
Hardware Mode 6 data flow is shown in
routed to the AES3 transmitter.
The transmitted channel status, user, and validity data may be input in two alternative methods, determined
by the state of the CEN pin. Mode 6A is selected when the CEN pin is low. In mode 6A, the user data and
validity bit are input via the U and V pins, clocked by both edges of ILRCK. The channel status data is de-
rived from the state of the COPY/C, ORIG, EMPH, and AUDIO pins.
ORIG pins map to channel status bits. In consumer mode, the transmitted category code shall be set to
Sample Rate Converter (0101100b).
Mode 6B is selected when the CEN pin is high. In mode 6B, the channel status, user data and validity bit
are input serially via the COPY/C, U, and V pins. These pins are clocked by both edges of ILRCK (if the port
is in Master mode).
The channel status block pin (TCBL) may be an input or an output, determined by the state of the TCBLD
pin. The serial audio input port data format is selected as shown in
slave by the state of the APMS input pin.
The following pages contain detailed pin descriptions for Hardware mode 6.
ILRCK
ISCLK
SDIN
Power supply pins (VD+, VA+, DGND, AGND) & the reset pin (RST)
are omitted from this diagram. Please refer to the Typical Connection Diagram for hook-up details.
Figure 20
VD+
APMS
DFC0
Serial
Audio
Input
Figure 29. Hardware Mode 6 - AES3 Transmitter Only
SFMT1 SFMT0
VD+
shows the timing requirements.
DFC1
VD+
S/AES
Figure
COPY/C ORIG EMPH AUDIO TCBL
VD+
29. Audio data is input via the serial audio input port and
H/S
C, U, V Data Buffer
FILT
Table
Table 15
Output
Clock
Source
AES3
Encoder
& Tx
OMCK
15, and may be set to master or
TCBLD
shows how the COPY/C and
TXP
TXN
CEN
U
V
CS8420
DS245F4