ADAU1445 Analog Devices, ADAU1445 Datasheet - Page 66

• Manufacturer Part Number: ADAU1445
• Manufacturer: Analog Devices

Specifications of ADAU1445

• Instructions/cycles: 3584
• Digital I/o Channels: 24/24
• Analog I/o Channels: 0/0
• Product Description: Digital audio processor with flexible audio routing matrix, 8 × 2-channel ASRC

ADAU1442/ADAU1445/ADAU1446
S/PDIF MODES AND SETTINGS
Table 54. Addresses of S/PDIF Modes Registers
Decimal
57536
57537
57538
57539
57540
57541
57542
57543
57544
57545
57546
57547
57548
S/PDIF Receiver—Read Auxiliary Output Register
(Address 0xE0C0)
Table 55. Bit Descriptions of Register 0xE0C0
Bit Position
[15:12]
11
10
9
8
[7:2]
[1:0]
This is a read-only register. It allows the S/PDIF auxiliary
output (including channel status, user data, and validity bit)
to be read.
Address
Hex
E0C0
E0C1
E0C2
E0C3
E0C4
E0C5
E0C6
E0C7
E0C8
E0C9
E0CA
E0CB
E0CC
Name
S/PDIF receiver—read
auxiliary output
S/PDIF transmitter—
on/off switch
S/PDIF read channel
status, Byte 0
S/PDIF read channel
status, Byte 1
S/PDIF read channel
status, Byte 2
S/PDIF read channel
status, Byte 3
S/PDIF read channel
status, Byte 4
S/PDIF word length
control
Auxiliary outputs—set
enable mode
S/PDIF lock bit
detection
Set hot enable
Read enable auxiliary
output
S/PDIF loss-of-lock
behavior
Readback Data
Reserved
Virtual LRCLK
Block start
Channel status
User data
Reserved
Validity
Read/Write
Word Length
16 bits (2 bytes)
16 bits (2 bytes)
16 bits (2 bytes)
16 bits (2 bytes)
16 bits (2 bytes)
16 bits (2 bytes)
16 bits (2 bytes)
16 bits (2 bytes)
16 bits (2 bytes)
16 bits (2 bytes)
16 bits (2 bytes)
16 bits (2 bytes)
16 bits (2 bytes)
Rev. C | Page 66 of 92
S/PDIF Transmitter—On/Off Switch Register
(Address 0xE0C1)
Table 56. Bit Descriptions of Register 0xE0C1
Bit
Position
[15:1]
0
This is a single-bit register. Setting Bit 0 to 1 switches the
S/PDIF transmitter on; setting it to 0 switches the transmitter
off for power savings.
S/PDIF Read Channel Status Register, Bytes[4:0]
(Address 0xE0C2 to Address 0xE0C6)
Table 57. Addresses of S/PDIF Read Channel Status Register
Decimal
57538
57539
57540
57541
57542
An S/PDIF stream contains channel status bits (after the audio
bits), which contain information such as sample rates, word
lengths, and time stamps. The full channel status information
contained in the stream is 24 bytes wide for each channel (that
is, 48 bytes in total). The ADAU1442/ADAU1445/ADAU1446
make the first five bytes of the left channel available through
I
S/PDIF Word Length Control Register (Address 0xE0C7)
Table 58. Bit Descriptions of Register 0xE0C7
Bit
Position
[15:2]
[1:0]
The word length of the audio data decoded from the S/PDIF
stream can be controlled using this register. Setting Bits[1:0] to 11 is
useful in cases where the S/PDIF stream can come from either a
CD or a DVD. From a CD the word length is 16 bits, and from a
DVD the word length is 24 bits. This information is contained in
the channel status bits and can be used to automatically ignore
the least significant byte, if required.
2
C/SPI.
Description
Reserved
S/PDIF transmitter—on/off switch
0 = S/PDIF transmitter disabled
1 = S/PDIF transmitter enabled
Description
Reserved
Word length
00 = 24 bit
01 = 20 bit
10 = 16 bit
11 = as decoded from the S/PDIF channel
status bits
Address
Hex
E0C2
E0C3
E0C4
E0C5
E0C6
Register
Byte 0
Byte 1
Byte 2
Byte 3
Byte 4
Default
0
Default
00